Semiconductor integrated circuit device
AssigneeKabushiki Kaisha Toshiba
InventorsYuui Shimizu, Kenji Tsuchida
Life of this patent
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Abstract
A semiconductor integrated circuit device includes a main memory cell array, redundant memory cell array, write current source, a common node connected to the write current source, a first selector connected between the common node and one-side ends of main write wirings and a second selector connected between the common node and one-side ends of redundant write wirings. The redundant memory cell array is arranged in a position apart from the main memory cell array and the write current source is commonly used by the main memory cell array and redundant memory cell array via the common node.
Claims20
A semiconductor integrated circuit device comprising:
- a main memory cell array having memory cells arranged in a matrix form and including at least one magneto-resistance effect element;
- a redundant memory cell array having memory cells arranged in a matrix form and including at least one magneto-resistance effect element used to compensate for a fault occurring in the main memory cell array, the redundant memory cell array being formed independently of the main memory cell array and arranged in a position apart from the main memory cell array;
- main write wirings arranged on the main memory cell array;
- redundant write wirings arranged on the redundant memory cell array;
- a write current source;
- a common node connected to the write current source;
- a first selector connected between the common node and one-side ends of the main write wirings;
- a second selector connected between the common node and one-side ends of the redundant write wirings;
- a third selector connected to the other ends of the main write wirings;
- and
- a fourth selector connected to the other ends of the redundant write wirings.
A semiconductor integrated circuit device comprising:
- a main memory cell array having memory cells arranged in a matrix form and including at least one magneto-resistance effect element;
- a redundant memory cell array having memory cells arranged in a matrix form and including at least one magneto-resistance effect element used to compensate for a fault occurring in the main memory cell array, the redundant memory cell array being arranged in a position apart from the main memory cell array;
- main write word lines arranged on the main memory cell array;
- main bit lines arranged on the main memory cell array;
- redundant write word lines arranged on the redundant memory cell array;
- redundant bit lines arranged on the redundant memory cell array;
- a write current source for the write word lines;
- a common node for the write word lines connected to the write current source for the write word lines;
- a first selector connected between the common node for the write word lines and one-side ends of the main write word lines;
- a second selector connected between the common node for the write word lines and one-side ends of the redundant write word lines;
- a third selector connected to the other ends of the main write word lines;
- a fourth selector connected to the other ends of the redundant write word lines;
- a write current source for the bit lines;
- a common node for the bit lines connected to the write current source for the bit lines;
- a fifth selector connected between the common node for the bit lines and one-side ends of the main bit lines;
- a sixth selector connected between the common node for the bit lines and one-side ends of the redundant bit lines;
- a seventh selector connected to the other ends of the main bit lines;
- and
- an eighth selector connected to the other ends of the redundant bit lines.
Dependencies are inferred from the claim text.