Multiple match detection circuit and method
AssigneeMosaid Technologies Incorporated
InventorsStanley Jeh-Chun Ma, Peter P. Ma
Life of this patent
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Abstract
A multiple matchline sense circuit for detecting a single, more than one, or no match conditions during a search-and-compare operation of a content addressable memory is disclosed. The circuit compares the rising voltage rate of a multiple matchline to the rising voltage rate of a reference multiple matchline in order to generate a multibit result representing one of the three conditions. The circuit generates a self-timed control signal to end the search-and-compare operation, and to set the circuit to a precharge state.
Claims20
A sensing circuit for detecting a voltage, comprising:
- a sense line;
- a current source operatively connected to the sense line, the current source switching between an off state and an on state for changing a sense line voltage from a first voltage level to a second voltage level,
- an amplifier for sensing a change in the sense line voltage to the second voltage level and for providing an amplified signal corresponding thereto;
- and
- a detection circuit for providing a multibit output based on a difference in delay between the amplified signal changing from the first voltage level to the second voltage level and a reference signal changing from the first voltage level to the second voltage level.
A method for detecting a voltage level, comprising the steps of:
- providing current to a sense line and a dummy sense line for changing a sense line and dummy sense line voltage level from a first voltage level to a second voltage level;
- detecting the transition of the sense line and dummy sense line from the first voltage level to the second voltage level;
- inhibiting current from the sense line and the dummy sense line when either the sense line or the dummy sense line reaches the second voltage level;
- and
- providing a multibit output based on a difference in delay between the sense line changing from the first voltage level to the second voltage level and a reference signal changing from the first voltage level to the second voltage level.
A content addressable memory comprising:
- an array of content addressable memory cells arranged in rows and columns;
- an address decoder;
- data access circuitry;
- and
- a sensing circuit having a multiple match line;
- a current source operatively connected to the multiple match line, the current source switching between an off state and an on state for changing the multiple match line from a first voltage level to a second voltage level;
- an amplifier for detecting the second voltage level for providing an amplified signal corresponding thereto;
- and a detection circuit for providing an output corresponding to a delay between the sense line changing from the first voltage level to the second voltage level and a reference signal changing from the first voltage level to the second voltage level.
Dependencies are inferred from the claim text.