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US 7,095,478 B2Granted
Liquid crystal display device and method for fabricating thereof
AssigneeSemiconductor Energy Laboratory Co., Ltd.
InventorsHongyong Zhang, Takeshi Fukunaga
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Abstract
To provide a technology for fabricating a high image quality liquid crystal display device, a set range of a cell gap for holding a liquid crystal layer is limited in accordance with a distance of a pixel pitch in which specifically, the cell gap is set to be a distance of one tenth of the pixel pitch, whereby the high image quality liquid crystal display device with no occurrence of image display failure caused by disturbances of an electric field such as disclination, can be realized.
Claims74
An electric device comprising:
- a plurality of gate lines and a plurality of data lines arranged in a matrix form over a substrate;
- a plurality of thin film transistors over said substrate, each thin film transistor arranged at a pixel area surrounded by adjacent two of said gate lines and adjacent two of said data lines;
- an interlayer insulating film comprising silicon over said thin film transistors;
- a flattering film over said interlayer insulating film;
- a plurality of pixel electrodes over said flattering film, each connecting to a drain electrode of the corresponding thin film transistor;
- an opposed substrate comprising an opposed electrode on a surface thereof;
- and at least one spacer interposed between said substrate and said opposed substrate,
- wherein a pixel pitch of said pixel area is 40 μm or less, and
- wherein a thickness of said spacer in a direction vertical to said substrate and said opposed substrate is 4 μm or less.
6 more elements
A method of fabricating an electric device comprising the steps of:
- forming a plurality of gate lines and a plurality of data lines arranged in a matrix form over a substrate;
- forming a plurality of thin film transistors over said substrate, each thin film transistor arranged at a pixel area surrounded by adjacent two of said gate lines and adjacent two of said data lines;
- forming a first interlayer film comprising an insulating material containing silicon over said thin film transistors;
- forming a second interlayer film over said first interlayer film;
- forming a plurality of pixel electrodes over said flattering film, each connecting to a drain electrode of the corresponding thin film transistor;
- and forming an opposed substrate comprising an opposed electrode on a surface thereof,
- wherein a pixel pitch of said pixel area is 40 μm or less,
- wherein an interval between said substrate and said opposed substrate is 4 μm or less, and
- wherein a stepped difference of said pixel electrode formed over a circumference of said drain electrode is 0.3 μm or less.
6 more elements
An electric device comprising:
- a plurality of gate lines and a plurality of data lines arranged in a matrix form over a substrate;
- a plurality of thin film transistors over said substrate, each of said thin film transistor arranged at a pixel area surrounded by adjacent two of said gate lines and adjacent two of said data lines;
- an interlayer insulating film comprising silicon over said thin film transistors;
- a flattering film over said interlayer insulating film;
- a plurality of pixel electrodes over said flattering film, each pixel electrode formed over the corresponding thin film transistor and connected to a drain electrode of said thin film transistor;
- and
- an opposed substrate comprising at least an opposed electrode on a surface thereof,
- wherein an interval between said substrate and said opposed substrate is 4 μm or less, and
- wherein a stepped difference of said pixel electrode formed over a circumference of said drain electrode is 0.3 μm or less.
6 more elements
An electric device comprising:
- a plurality of gate lines and a plurality of data lines arranged in a matrix form over a substrate;
- a plurality of thin film transistors formed over said substrate, each of said thin film transistors arranged at a pixel area surrounded by adjacent two of said gate lines and adjacent two of said data lines;
- an interlayer insulating film comprising silicon formed over said thin film transistors;
- a flattering film formed over said interlayer insulating film;
- a plurality of black matrices, each black matrix formed over a corresponding thin film transistor;
- a plurality of pixel electrodes, each pixel electrode formed over said flattering film and connected to a drain electrode of said thin film transistor;
- and an opposed substrate comprising at least an opposed electrode on a surface thereof,
- wherein a pixel pitch of said pixel area is 40 μm or less,
- wherein an interval between said substrate and said opposed substrate is 4 μm or less, and
- wherein a stepped difference of said pixel electrode formed over a circumference of said drain electrode is 0.3 μ or less.
7 more elements
An electric device comprising:
- a plurality of gate lines and a plurality of data lines arranged in a matrix form over a substrate;
- a plurality of thin film transistors formed over said substrate, each of said thin film transistors arranged at a pixel area surrounded by adjacent two of said gate lines and adjacent two of said data lines;
- an interlayer insulating film comprising silicon formed over said thin film transistors;
- a flattering film formed over said interlayer insulating film;
- a plurality of black matrices, each black matrix formed over a corresponding thin film transistor;
- a plurality of pixel electrodes, each pixel electrode formed over said flattering film and connected to a drain electrode of said thin film transistor;
- and an opposed substrate comprising at least an opposed electrode on a surface thereof,
- wherein an interval between said substrate and said opposed substrate is 4 μm or less, and
- wherein a stepped difference of said pixel electrode formed over a circumference of said drain electrode is 0.3 μm or less.
6 more elements
An electric device comprising:
- a plurality of gate lines and a plurality of data lines arranged in a matrix form over a substrate;
- a plurality of switching elements over said substrate, each switching element arranged at a pixel area surrounded by adjacent two of said gate lines and adjacent two of said data lines;
- an interlayer insulating film comprising silicon over said switching elements;
- a flattering film over said interlayer insulating film;
- a plurality of pixel electrodes over said flattering film, each pixel electrode connecting to a drain electrode of the corresponding switching element;
- and
- an opposed substrate comprising at least an opposed electrode on a surface thereof,
- wherein a pixel pitch of said pixel area is 40 μm or less, and
- wherein an interval between said substrate and said opposed substrate is 4 μm or less, and
- wherein a stepped difference of said pixel electrode formed over a circumference of said drain electrode is 0.3 μ or less.
7 more elements
An electric device comprising:
- a plurality of gate lines and a plurality of data lines arranged in a matrix form over a substrate;
- a plurality of switching elements over said substrate, each of said switching element arranged at a pixel area surrounded by adjacent two of said gate lines and adjacent two of said data lines;
- an interlayer insulating film comprising silicon over said switching elements;
- a flattering film over said interlayer insulating film;
- a plurality of pixel electrodes over said flattering film, each pixel electrode formed over the corresponding switching element and connected to a drain electrode of said switching element;
- and
- an opposed substrate comprising at least an opposed electrode on a surface thereof,
- wherein an interval between said substrate and said opposed substrate is 4 μm or less, and
- wherein a stepped difference of said pixel electrode formed over a circumference of said drain electrode is 0.3 μm or less.
6 more elements
Dependencies are inferred from the claim text.