Graphics display architecture and control chip set thereof

A graphics display architecture, comprising:

• a first graphics adapter slot;
• a second graphics adapter slot;
• and
• a control chip set, electrically coupled to both the first graphics adapter slot and the second graphics adapter slot, wherein said control chip set comprising a plurality of multi-defined pins connects to pins of said first graphics adapter slot and pins of said second graphics adapter slot with a shared bus, and said control chip set uses a shared bus to connect an AGP slot and a PCIE slot and serves to send/receive a signal complied with said first graphics adapter as a first graphics adapter is plugged in said first graphics adapter slot, and said control chip set serves to send/receive a signal complied with said second graphics adapter as a second graphics adapter is plugged in said second graphics adapter slot.

A control chip set with a plurality of multi-defined pins and suitable for a graphics display architecture, comprising:

• an AGP core circuit for controlling and sending/receiving a signal complied with an AGP interface specification;
• a PCIE core circuit, for controlling and sending/receiving a signal complied with a PCIE interface specification;
• a Graphics (Gfx) core circuit, for controlling and sending/receiving a signal complied with a Gfx interface specification;
• and
• a multiplexor/demultiplexor, coupled to said AGP core circuit, said PCIE core circuit, and said Gfx core circuit, and said multiplexor/demultiplexor selectively either transmitting a signal from one of said AGP core circuit, said PCIE core circuit, and said Gfx core circuit to a plurality of multi-defined pins or transmitting a signal of the multi-defined pins to one of said AGP core circuit, said PCIE core circuit, and said Gfx core circuit.