DA converter circuit provided with DA converter of segment switched capacitor type

A ⊖Σ AD modulator comprising:

• a DA converter circuit;
• a subtracter for subtracting a signal outputted from the DA converter circuit from an inputted analog signal and outputting a signal having a subtraction result;
• a low-pass filter for performing a predetermined low-pass filtering process onto the analog signal outputted from the subtracter and outputting a filtered signal;
• and
• an AD converter circuit for AD-converting the analog signal outputted from the low-pass filter into a digital signal and outputting the AD-converted digital signal and further outputting the digital signal to the subtracter via the DA converter circuit,
• wherein said DA converter circuit includes a DA converter of segment switched capacitor type,
• wherein said DA converter comprising:
• (a) an operational amplifier having a feedback capacity;
• (b) a plurality of M=2L capacitors which are connected in parallel to each other so as to supply electric charges to the operational amplifier;
• (c) an electrically charging switch for switching over between performing and not performing of electrically charging electric charges onto the respective capacitors;
• and
• (d) an electrically discharging switch for switching over between performing and not performing of electrically discharging electric charges from the respective capacitors, and
• wherein the DA converter circuit further comprises:
• a switch device for performing either electrically charging, the electrically discharging operation, grounding, or polarity inversion onto the respective capacitors;
• and
• a controller for controlling the electrically charging switch, the electrically discharging switch and the switch device so as to execute a process of second-order DWA algorithm for performing a second-order noise shaping of a non-linearity of the DA converter circuit for a low-pass ΔΣ AD modulator, using the following operations:
• (A) a “+2” operation for performing the electrically charging and the electrically discharging twice onto the respective capacitors for a predetermined time interval to generate an output voltage which is a voltage of +2 times a predetermined reference output voltage;
• (B) a “+1” operation for performing the electrically charging and the electrically discharging once onto the respective capacitors for the time interval to generate an output voltage which is a voltage of +1 times the reference output voltage;
• (C) a “0” operation for not performing any electrically charging and electrically discharging onto the respective capacitors for the time interval to generate an output voltage which is a voltage of a grounding electric potential;
• and
• (D) a “−1” operation for performing the electrically charging once onto the respective capacitors and thereafter inverting polarities of the respective capacitors for the time interval to generate an output voltage which is a voltage of −1 times the reference output voltage.