Programmable gain instrumentation amplifier having improved dielectric absorption compensation and common mode rejection ratio

An instrumentation amplifier for use in a measurement device, the instrumentation amplifier comprising:

• a negative input terminal;
• a positive input terminal;
• a first op-amp comprising a noninverting input terminal, an inverting input terminal, and an output terminal, wherein one of the input terminals of the first op-amp is coupled to the negative input terminal of the instrumentation amplifier;
• and
• a common mode rejection ratio (CMRR) enhancement circuit coupled to the output terminal of the first op-amp, wherein the CMRR enhancement circuit is operable to delay an input signal received at the negative input terminal a particular amount such that the input signal received at the negative input terminal will be in phase with an input signal received at the positive input terminal of the instrumentation amplifier, to improve the CMRR of the instrumentation amplifier.

A data acquisition device, comprising:

• one or more analog-to-digital converters (ADCs) operable to convert received analog data into digital data;
• and
• a programmable gain instrumentation amplifier (PGIA) coupled to the one or more ADCs, the PGIA comprising:
• a negative input terminal;
• an output terminal;
• a first op-amp comprising a noninverting input terminal, an inverting input terminal, and an output terminal, wherein one of the input terminals of the first op-amp is coupled to the negative input terminal of the PGIA;
• a current-to-voltage (I-V) converter comprising a first input terminal, a second input terminal, and an output terminal, wherein the output terminal of the I-V converter is coupled to the output terminal of the PGIA;
• a first dielectric absorption (DA) compensation circuit coupled to the output terminal of the first op-amp, wherein the first DA compensation circuit is operable to generate a first DA compensation signal which is derived from an input step signal received at the negative input terminal of the PGIA;
• a second DA compensation circuit coupled to one of the input terminals of the I-V converter, wherein the second DA compensation circuit is operable to generate a second DA compensation signal and provide the second DA compensation signal to the I-V converter, wherein the first and second DA compensation signals are operable to reduce dielectric absorption and improve a step response of the PGIA;
• and
• a common mode rejection ratio (CMRR) enhancement circuit coupled in parallel to the first DA compensation circuit, wherein the CMRR enhancement circuit is operable to delay an input received at the negative input terminal of the PGIA to improve a CMRR of the PGIA.

A PGIA for use in a data acquisition device, the PGIA comprising:

• a negative input terminal;
• an output terminal;
• a first op-amp comprising a noninverting input terminal, an inverting input terminal, and an output terminal, wherein one of the input terminals of the first op-amp is coupled to the negative input terminal of the PGIA;
• a current-to-voltage (I-V) converter comprising a first input terminal, a second input terminal, and an output terminal, wherein the output terminal of the I-V converter is coupled to the output terminal of the PGIA;
• a first current source operable to provide a biasing current to a signal path of the PGIA;
• a first DA compensation circuit coupled between the output terminal of the first op-amp and the first current source, wherein the first DA compensation circuit comprises a first resistor, a second resistor, a third resistor, and a first capacitor, and wherein the second resistor is coupled in series with the first capacitor and the second resistor is also coupled to a junction of the first and third resistors;
• a second DA compensation circuit coupled to one of the input terminals of the I-V converter, wherein the second DA compensation circuit comprises a fourth resistor, a fifth resistor, and a second capacitor, and wherein the second capacitor is coupled between the one of the input terminals of the I-V converter and a junction of the fourth and fifth resistors;
• and
• a CMRR enhancement circuit coupled in parallel to the first DA compensation circuit, wherein the CMRR enhancement circuit comprises a sixth resistor coupled in series to a third capacitor, wherein the sixth resistor is coupled to the output terminal of the first op-amp and the third capacitor is coupled to the first current source.

A data acquisition device, comprising:

• one or more analog-to-digital converters (ADCs) operable to convert received analog data into digital data;
• and
• a PGIA coupled to the one or more ADCs, the PGIA comprising:
• a negative input terminal;
• a positive input terminal;
• an output terminal;
• a first op-amp comprising a noninverting input terminal, an inverting input terminal, and an output terminal, wherein one of the input terminals of the first op-amp is coupled to the negative input terminal of the PGIA;
• a current-to-voltage (I-V) converter comprising a first input terminal, a second input terminal, and an output terminal, wherein the output terminal of the I-V converter is coupled to the output terminal of the PGIA;
• a first current source operable to provide a biasing current to a signal path of the PGIA;
• a first DA compensation circuit coupled between the output terminal of the first op-amp and the first current source, wherein the first DA compensation circuit is operable to generate a first DA compensation signal which is derived from an input step signal received at the negative input terminal of the PGIA;
• a second DA compensation circuit coupled to one of the input terminals of the I-V converter, wherein the second DA compensation circuit is operable to generate a second DA compensation signal and provide the second DA compensation signal to the I-V converter, wherein the first and second DA compensation signals are operable to reduce dielectric absorption and improve a step response of the PGIA;
• and
• a CMRR enhancement circuit coupled in parallel to the first DA compensation circuit, wherein the CMRR enhancement circuit is operable to delay an input signal received at the negative input terminal a particular amount such that the input signal received at the negative input terminal will be in phase with an input signal received at the positive input terminal of the PGIA, to improve the CMRR of the PGIA.