Bias circuit

A bias circuit comprising:

• an output node for outputting an output current;
• an internal node;
• a feedback amplifier comparing a first reference voltage with a voltage on the internal node and outputting a feedback signal;
• a current source controlled by the feedback signal;
• a first differential transistor connected between the internal node and the current source, the first differential transistor receiving a second reference voltage;
• a second differential transistor connected to the current source, the second differential transistor receiving the second reference voltage, the second differential transistor having a dimension that is different from that of the first differential transistor;
• a first resistive element connected to the internal node;
• a second resistive element connected to the second differential transistor;
• and
• an output transistor having a gate connected to receive the feedback signal and a drain connected to the output node.

A bias circuit comprising:

• an output node outputting an output signal;
• an internal node on which an internal voltage is applied;
• a feedback amplifier comparing a first reference voltage with the internal voltage;
• a current source connected to a first potential source, the current source providing a constant current in response to the feedback signal;
• a first differential transistor connected to the current source, the first differential transistor receiving a second reference voltage;
• a second differential transistor connected to the current source, the second differential transistor receiving the second reference voltage, the second differential transistor having a dimension that is different from that of the first differential transistor;
• a first resistive transistor connected between the first differential transistor and a second potential source;
• a second resistive transistor connected between the second differential transistor and the second potential source, the second resistive transistor having a first gate;
• a first mirror transistor having a second gate connected to the first gate, the first mirror transistor connected between the internal node and the second potential source;
• and
• a second mirror transistor having a third gate connected to the first gate, the second mirror transistor connected between the output node and the second power source.