Voltage generator
AssigneeOki Electric Industry Co., Ltd.
InventorHitoshi Yamada
Life of this patent
Estimating the term…
Abstract
When the substrate bias voltage Vbb lowers by the pumping operation of the charge pump circuit, a drain-to-source resistance of the N-transistor becomes high. When a first power supply voltage Vcc is set at high value, a drain-to-source current of the N-transistor increases (I+ΔI1), however the drain-to-source current decreases (I+ΔI1−ΔI2) by the increase of the drain-to-source current owing to the substrate bias effect so that the increase of the potential of the node N34 caused by the increase of the first power supply voltage VCC is restrained. As a result, a reference level of the substrate bias voltage Vbb does not largely lower than the reference level of the substrate bias voltage. Vbb when the first power supply voltage VCC is in a standard level.
Claims24
A voltage generator comprising:
- a voltage generator circuit that raises a level of an output voltage when a voltage level detection signal is a first logical level and that lowers the level of the output voltage when the voltage level detection signal is a second logical level;
- a first voltage level detection circuit generating a first detection signal in accordance with a first detection level, wherein the first voltage level detection circuit includes
- a logical level decision circuit that provides the first detection signal responsive to a potential at a detection node,
- a first current mirror circuit connected to a first potential source, the detection node and the voltage generator circuit, wherein the first current mirror circuit includes a first transistor having a first terminal connected to the first potential source, a second terminal, and a control terminal, and a second transistor having a first terminal connected to the detection node, a second terminal connected to a predetermined level that is changed according to the level of the output voltage, and a control terminal connected to the control terminal of the first transistor, and
- a second current mirror circuit connected to a second potential source, the detection node and the first current mirror circuit;
- a second voltage level detection circuit generating a second detection signal in accordance with a second detection level that is lower than the first detection level;
- and
- a selection circuit connected to the first and second voltage level detection circuits,
- wherein the selection circuit outputs a signal equivalent to the first detection signal as the voltage level detection signal when a power supply voltage level is equal to or higher than a first voltage level or when the power supply voltage level is equal to or lower than a second voltage level that is lower than the first voltage level, and
- wherein the selection circuit outputs a signal equivalent to the second detection signal as the voltage level detection signal when the power supply voltage level is lower than the first voltage level and higher than the second voltage level.
A voltage generator comprising:
- a semiconductor substrate;
- a voltage generator circuit connected to the semiconductor substrate, the voltage generator supplying a predetermined voltage to the semiconductor substrate in response to a control signal;
- a first voltage level detection circuit connected to the semiconductor substrate, the first voltage level detection circuit generating a first detection signal when a voltage level of the semiconductor substrate is lower than a first voltage level, wherein the first voltage level detection circuit includes
- a buffer circuit connected to the voltage generator circuit, the buffer circuit generating the first detection signal,
- a first current mirror circuit connected to the buffer circuit, the semiconductor substrate and a first potential source, the first current mirror circuit including a first NMOS transistor having a source connected to the semiconductor substrate, a drain connected to the buffer circuit, and a gate, and a second NMOS transistor having a source connected to the first potential source, a drain and a gate connected to the gate of the first NMOS transistor, and
- a second current mirror circuit connected to the buffer circuit, a second potential source and the drain of the second NMOS transistor;
- a second voltage level detection circuit connected to the semiconductor substrate, the second voltage level detection circuit generating a second detection signal when the voltage level of the semiconductor substrate is lower than a second voltage level that is lower than the first voltage level;
- and
- a selection circuit connected to the first and second voltage level detection circuits,
- wherein the selection circuit outputs a signal equivalent to the first detection signal as the control signal when a power supply voltage level is equal to or higher than the first voltage level, or when the power supply voltage level is equal to or lower than the second voltage level, and
- wherein the selection circuit outputs a signal equivalent to the second detection signal as the control signal when the power supply voltage level is lower than the first voltage level and higher than the second voltage level.
A voltage generator comprising:
- a voltage generator circuit that raises a level of an output voltage when a voltage level detection signal is a first logical level and that lowers the level of the output voltage when the voltage level detection signal is a second logical level;
- a first voltage level detection circuit generating a first detection signal in accordance with a first detection level;
- a second voltage level detection circuit generating a second detection signal in accordance with a second detection level that is lower than the first detection level, wherein the second voltage level detection circuit includes
- a logical level decision circuit that provides the second detection signal in response to a potential at a detection node,
- a first transistor having a first terminal connected to a first potential source, a second terminal connected to the detection node and a control terminal connected to the detection node, and
- a second transistor having a first terminal, a second terminal connected to the detection node, and a control terminal connected to the detection node;
- and
- a selection circuit connected to the first and second voltage level detection circuits,
- wherein the selection circuit outputs a signal equivalent to the first detection signal as the voltage level detection signal when a power supply voltage level is equal to or higher than a first voltage level or when the power supply voltage level is equal to or lower than a second voltage level that is lower than the first voltage level, and
- wherein the selection circuit outputs a signal equivalent to the second detection signal as the voltage level detection signal when the power supply voltage level is lower than the first voltage level and higher than the second voltage level.
Dependencies are inferred from the claim text.