PVT-compensated clock distribution
AssigneeRambus Inc.
InventorsHuy Nguyen, Roxanne Vu, Benedict Lau
Life of this patent
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Abstract
Described are methods and systems for distributing low-skew, predictably timed clock signals. A clock distribution network includes a plurality of dynamically adjustable clock buffers. A control circuit connected to each clock buffer controls the delays through the clock buffers in response to process, voltage, and temperature variations, and consequently maintains a relatively constant signal-propagation delay through the network. In one embodiment, each clock buffer includes skew-offset circuitry that adds to or subtracts from the PVT compensated delay values provided by the PVT control circuit to simplify clock skew minimization.
Claims16
An integrated circuit comprising:
- a. a clock tree having:
- i. a clock root node;
- ii. first and second clock destination nodes;
- iii. a first plurality of adjustable clock buffers disposed in series between the root node and the first clock destination node, each of the first plurality of adjustable clock buffers including a clock-adjust port;
- and
- iv. a second plurality of adjustable clock buffers disposed in series between the root node and the second clock destination node, each of the second plurality of adjustable clock buffers including a clock-adjust port;
- and
- b. a control circuit coupled to the clock-adjust ports of the first and second pluralities of clock buffers, the control circuit having:
- i. an adjustable delay section having an input node coupled to the clock root node, a delay-section output node, and a delay-adjust port;
- and
- ii. a phase detector coupled to the clock root node, the delay-section output node, and the delay-adjust port.
A clock distribution network comprising:
- a. a clock source providing a clock signal of a clock frequency;
- and
- b. a clock tree having:
- i. a root node coupled to the clock source and receiving the clock signal;
- ii. a plurality of clock destination nodes;
- and
- iv. at least one dynamically adjustable clock buffer disposed between the root node and at least one of the plurality of destination nodes, the clock buffer exhibiting a delay and conveying the clock signal to the at least one destination node and including at least one clock-adjust terminal;
- and
- c. a control circuit coupled to the clock-adjust terminals and developing a clock-adjust signal on the clock-adjust terminal in response to temperature and supply-voltage fluctuations changes;
- d. wherein the control circuit maintains the delay through the clock buffer in inverse proportion to the clock frequency;
- e. wherein the control circuit includes at least one adjustable delay element coupled to the root node and receiving the clock signal and a phase detector having a first and second phase-detector input nodes separated by the adjustable delay element.
A clock distribution network comprising:
- a. a clock source providing a clock signal of a clock frequency;
- and
- b. a clock tree having:
- i. a root node coupled to the clock source and receiving the clock signal;
- ii. a plurality of clock destination nodes;
- and
- iv. at least one dynamically adjustable clock buffer disposed between the root node and at least one of the plurality of destination nodes, the clock buffer exhibiting a delay and conveying the clock signal to the at least one destination node and including at least one clock-adjust terminal;
- and
- c. a control circuit coupled to the clock-adjust terminals and developing a clock-adjust signal on the clock-adjust terminal in response to temperature and supply-voltage fluctuations changes;
- d. wherein the control circuit maintains the delay through the clock buffer in inverse proportion to the clock frequency;
- e. the control circuit including an adjustable delay element coupled to the clock source and exhibiting a first signal propagation delay, wherein the dynamically adjustable clock buffer exhibits a second signal propagation delay, and wherein the control circuit maintains the ratio of the first and second signal propagation delays independent of the frequency of the clock signal.
Dependencies are inferred from the claim text.