Circuit arrangement for the provision of an output signal with adjustable flank pitch

Circuitry for adjusting a slope of an edge of an output signal, the circuitry comprising:

• a ramp signal generator to output a trapezoidal signal;
• drivers to respond to the trapezoidal signal by outputting control signals, the drivers having different switching thresholds;
• a set of top transistors, each of the top transistors comprising a gate to receive a control signal from a corresponding driver, a source connected to a supply potential, and a drain connected to an output;
• and
• a set of bottom transistors, each of the bottom transistors comprising a gate to receive a control signal from a corresponding driver, a source connected to a reference potential, and a drain connected to the output;
• wherein, at a rising edge of the trapezoidal signal, drivers corresponding to the bottom transistors are operable to output control signals to sequentially deactivate the bottom transistors and then drivers corresponding to the top transistors are operable to output control signals to sequentially activate the top transistors.

Circuitry comprising:

• a ramp signal generator to receive an input signal and to generate a trapezoidal signal based on the input signal;
• a circuit array to receive the trapezoidal signal and to generate control signals based on the trapezoidal signal;
• first output transistors having gates to receive a first set of the control signals, the first output transistors comprising a first top transistor and a first bottom transistor, the first top transistor having a source connected to a supply potential and a drain connected to an output, the first bottom transistor having a source connected to a reference potential and a drain connected to the output, the first top transistor and the first bottom transistor being gated by the first set of control signals to control a shape of an edge of an output signal at the output;
• and
• second output transistors having gates to receive a second set of the control signals, the second output transistors comprising a second top transistor and a second bottom transistor, the second top transistor having a source connected to the supply potential and a drain connected to the output, the second bottom transistor having a source connected to the reference potential and a drain connected to the output, the second top transistor and the second bottom transistor being gated by the second set of control signals to control the shape of the edge of the output signal;
• wherein the circuit array comprises first pre-drivers to generate control signals for the first output transistors and second pre-drivers to generate control signals for the second output transistors;
• and
• wherein at least two of the first and second output transistors have different switching thresholds, or at least two of the first and second pre-drivers have different switching thresholds.