Fast low drop out (LDO) PFET regulator circuit

A method of providing a regulated output voltage from a supply voltage source comprising:

• providing a field effect transistor (FET) regulator circuit comprising a regulating FET;
• providing a decision circuit coupled to the regulating FET;
• operating the regulating FET in a saturation mode of operation;
• and,
• upon operation of the regulating FET in a triode region providing increased signal gain to the regulating FET comprising:
• enabling operation of the decision circuit upon operation of the regulating FET in the triode region;
• and,
• providing a first boost current to the regulating FET results in an increase in a signal provided to the gate terminal thereof.

A method of providing a regulated output voltage from a supply voltage source comprising:

• providing a field effect transistor (FET) regulator circuit comprising a regulating FET;
• providing a decision circuit coupled to the FET regulator circuit;
• providing a first boost circuit coupled with the FET regulator circuit;
• operating the regulating FET in a saturation mode of operation;
• upon operation of the regulating FET in the triode region, enabling operation of the first boost circuit for providing a first boost current;
• enabling operation of the decision circuit;
• and,
• deciding using the decision circuit whether to provide the first boost current to the FET regulator circuit for resulting in an increase in a signal that is provided to the gate terminal of the regulating FET.

A low drop out (LDO) regulator circuit for providing a regulated output voltage from a supply voltage source comprising:

• an output port;
• a regulator circuit comprising a first FET having gate, drain and source terminals, the output port coupled to the drain terminal for providing the regulated output voltage therefrom, the first FET for operating in first mode of operation when a potential of the supply voltage source is above a predetermined potential;
• a voltage reference for providing a reference potential;
• a first long tail pair of transistors comprising first and second transistors having emitter, collector and base terminals;
• a second current source coupled to the base terminal of the second transistor from the first long tail pair of transistors;
• a first resistor disposed between the base terminal of the second transistor of the first long tail pair and the second current source and the drain terminal of the first FET and the output port, the second current source for sinking a second current in order to increase the potential of the regulated output voltage;
• a first current source connected to the emitter terminals for emitting a first current that is proportional to absolute temperature thereto, where the voltage reference is for providing a reference voltage to the base terminal of the first transistor of the first long tail pair of transistors;
• and,
• a decision circuit comprising a second FET having a gate terminal coupled to the gate terminal of the first FET for reducing a transimpedance of the first FET by controlling a provision of a first boost current for provision to the long tail pair when the potential of the supply voltage source is below the predetermined potential such that the first FET operates in a second mode of operation thereof and is for other than providing the first boost current when the potential of the supply voltage source is above the predetermined potential.