Ultra-drowsy circuit

A system, comprising:

• an antenna;
• a wireless node to couple to said antenna, said wireless node having a power reduction mode to reduce power to a memory element, said memory element comprising an ultra-drowsy state retention circuit comprising:
• a first and second pull-up transistors, said first pull-up transistor having a source coupled to a first power supply and a drain to output a first output signal, and said second pull-up transistor having a source coupled to said first power supply and a drain to output a second output sipnal;
• a set of four transistors arranged as a pair of cross coupled inverters which are coupled to a second power supply and a third power supply;
• first and second pass gate transistors, with each pass gate transistor having a gate to receive an input signal, with said first pass gate transistor having a source coupled to said drain for said first pull-up transistor and a drain coupled to said cross coupled inverters, and said second pass gate transistor having a source coupled to said drain for said second pull-up transistor and a drain coupled to said cross coupled inverters;
• and
• a power gate transistor having a gate coupled to said input signal, a drain coupled to said cross coupled inverters, and a source coupled to said second power supply.