Charge sharing reduction by applying intrinsic parallelism in complex dynamic domino type CMOS gates
AssigneeInternational Business Machines Corporation
InventorsMichael Haase, Wilhelm Haller, Rolf Sautter, Christoph Wandel
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Abstract
The present invention relates to dynamic hardware logic of computer processors. In particular, it relates to a method and respective system for operating a dynamic logic circuit implementing some predetermined logic function with reduced charge sharing. In order to further reduce charge sharing it is proposed to provide a predetermined number of pre-engineered switching arrangements (24, 26, 28) implementing the same logic function with a different combinatorial distribution of input variables (A, B, C), wherein each arrangement is connected between said precharged node of higher potential and a lower potential.
Claims8
A dynamic logic circuit having reduced charge sharing, the dynamic logic circuit comprising:
- a precharge circuit connected to an precharge node, the precharge circuit precharging the node to a first voltage level during a precharge period;
- a first logic circuit coupled to the precharge node, the first logic circuit comprising pre-engineered switching arrangements, the first logic circuit setting the precharge node to a second voltage level responsive to a predetermined combination of input signals during a non-precharge period, the first logic circuit comprising a plurality of pre-engineered switching arrangements a first pre-engineered switching arrangement comprising:
- a) a first transistor coupling a second node to the precharge node according to an input signal applied to a first gate of the first transistor, a second transistor coupling a third node to the second voltage level according to an input signal applied to a second gate of the second transistor and one or more third transistors coupling the second node to the third node according to one or more input signals applied to corresponding third gates of the one or more third transistors, the combination of the first transistor and the second transistor and the one or more third transistors performing a first predetermined logic function;
- b) a first input signal connected to the first gate of the first transistor;
- c) a second input signal connected to the second gate of the second transistor;
- and
- d) one or more third input signals connected to corresponding third gates of the one or more third transistors;
- a second pre-engineered switching arrangement comprising a fourth transistor coupling a fourth node to the precharge node according to an input signal applied to a fourth gate of the fourth transistor, a fifth transistor coupling a fifth node to the second voltage level according to an input signal applied to a fifth gate of the fifth transistor and one or more sixth transistors coupling the fourth node to the fifth node according to one or more input signal applied to corresponding sixth gates of the one or more sixth transistors, the combination of the fourth transistor and the fifth transistor and the one or more sixth transistors performing a second predetermined logic function wherein the second predetermined logic function is any one of the first predetermined logic function or a subset of the first predetermined logic function;
- the first input signal connected to any one of the fifth gate or one of the sixth gates, the first input signal not connected to the fourth gate;
- and
- the second input signal connected to any one of the fourth gate or one of the sixth gates, second input signal not connected to the fifth gate.
Dependencies are inferred from the claim text.