US 7,095,247 B1 · Configuring FPGAs and the like using one or more serial memory devices

Abstract

The configuration architecture for a programmable device, such as an FPGA, includes one or more memory devices connected directly to the FPGA such that the FPGA can be configured with configuration data stored in the memory devices without transmitting the configuration data via a controller connected between any of the memory devices and the FPGA. In one embodiment, the FPGA has an Serial Peripheral Interface (SPI) that is connected to the SPI interface of each of one or more SPI serial flash PROMs operating as boot PROMs. When there are two or more boot PROMs, each PROM stores a portion of the FPGA's configuration data and the FPGA interleaves the data from multiple boot PROMs to generate a serial configuration data bitstream. The present invention enables boot PROMs having different sizes and/or storing different amounts of configuration data to be simultaneously connected to an FPGA to support efficient configuration architectures.

Claims40

Dependent claims

A programmable device comprising a Serial Peripheral Interface (SPI) adapted to be connected in parallel to an SPI interface of each of two or more SPI serial memory devices such that the programmable device is adapted to receive a different portion of configuration data stored in each SPI serial memory device without transmitting the configuration data via a controller connected between the SPI serial memory devices and the programmable device.

A programmable device adapted to be connected in parallel to two or more memory devices such that the programmable device is adapted to receive configuration data stored in the two or more memory devices without transmitting the configuration data via a controller connected between any of the memory devices and the programmable device, wherein the programmable device is adapted to receive a different portion of the configuration data from each different memory device, and wherein one or more of (a)–(i):

(a) the programmable device has an SPI interface;
each memory device is an SPI serial memory device having an SPI interface;
and
the SPI interface of each SPI serial memory device is connected to the SPI interface of the programmable device;
(b) the programmable device is adapted to independently generate at least one command adapted to control operations of the memory devices during configuration of the programmable device;
(c) the programmable device is adapted to generate a message to inform the memory devices of a starting address to be used to transfer the configuration data stored in the memory devices to the programmable device;
(d) the programmable device is adapted to receive instructions to ignore data from a memory device;
(e) the programmable device is adapted to be instructed, based on information contained in the configuration data, as to how to interpret the different portions of the configuration data received from the different memory devices;
(f) the programmable device is adapted to process different amounts of configuration data received from different memory devices;
(g) the programmable device comprises:
a multiplexer (mux) adapted to interleave the configuration data from the two or more different memory devices;
and
a timing controller adapted to control the operations of the mux and to generate a configuration clock signal used to control the timing of the reading of the configuration data from the two or more different memory devices;
(h) each different portion of the configuration data from the corresponding memory device is received at a different configuration data input pin of the programmable device;
and
(i) each of one or more output pins of the programmable device is adapted to be connected to corresponding pins of all of the memory devices;
and
the programmable device has a configuration clock signal pin adapted to be connected to corresponding configuration clock signal pins of all of the memory devices such that configuration data is transmitted simultaneously from all of the memory devices to the programmable device.

15 more elements

An apparatus comprising:

a programmable device;
and
two or more memory devices, wherein:
the programmable device is connected in parallel to each memory device such that the programmable device is adapted to receive configuration data stored in the two or more memory devices without transmitting the configuration data via a controller connected between any of the memory devices and the programmable device, wherein the programmable device is adapted to receive a different portion of the configuration data from each different memory device, and wherein one or more of (a)–(i):
(a) the programmable device has an SPI interface;
each memory device is an SPI serial memory device having an SPI interface;
and
the SPI interface of each SPI serial memory device is connected to the SPI interface of the programmable device;
(b) the programmable device is adapted to independently generate at least one command adapted to control operations of the memory devices during configuration of the programmable device;
(c) the programmable device is adapted to generate a message to inform the memory devices of a starting address to be used to transfer the configuration data stored in the memory devices to the programmable device;
(d) the programmable device is adapted to receive instructions to ignore data from a memory device;
(e) the programmable device is adapted to be instructed, based on information contained in the configuration data, as to how to interpret the different portions of the configuration data received from the different memory devices;
(f) the programmable device is adapted to process different amounts of configuration data received from different memory devices;
(g) the programmable device comprises:
a multiplexer (mux) adapted to interleave the configuration data from the two or more different memory devices;
and
a timing controller adapted to control the operations of the mux and to generate a configuration clock signal used to control the timing of the reading of the configuration data from the two or more different memory devices;
(h) each different portion of the configuration data from the corresponding memory device is received at a different configuration data input pin of the programmable device;
and
(i) each of one or more output pins of the programmable device is adapted to be connected to corresponding pins of all of the memory devices;
and
the programmable device has a configuration clock signal pin adapted to be connected to corresponding configuration clock signal pins of all of the memory devices such that configuration data is transmitted simultaneously from all of the memory devices to the programmable device.

19 more elements

A method for configuring a programmable device, comprising:

simultaneously reading configuration data from two or more memory devices connected in parallel to the programmable device without transmitting the configuration data via a controller connected between any of the memory devices and the programmable device, wherein the programmable device receives a different portion of the configuration data from each different memory device;
and
configuring the programmable device using the configuration data, wherein one or more of (a)–(i):
(a) the programmable device has an SPI interface;
each memory device is an SPI serial memory device having an SPI interface;
and
the SPI interface of each SPI serial memory device is connected to the SPI interface of the programmable device;
(b) the programmable device is adapted to independently generate at least one command adapted to control operations of the memory devices during configuration of the programmable device;
(c) the programmable device is adapted to generate a message to inform the memory devices of a starting address to be used to transfer the configuration data stored in the memory devices to the programmable device;
(d) the programmable device is adapted to receive instructions to ignore data from a memory device;
(e) the programmable device is adapted to be instructed, based on information contained in the configuration data, as to how to interpret the different portions of the configuration data received from the different memory devices;
(f) the programmable device is adapted to process different amounts of configuration data received from different memory devices;
(g) the programmable device comprises:
a multiplexer (mux) adapted to interleave the configuration data from the two or more different memory devices;
and
a timing controller adapted to control the operations of the mux and to generate a configuration clock signal used to control the timing of the reading of the configuration data from the two or more different memory devices;
(h) each different portion of the configuration data from the corresponding memory device is received at a different configuration data input pin of the programmable device;
and
(i) each of one or more output pins of the programmable device is adapted to be connected to corresponding pins of all of the memory devices;
and
the programmable device has a configuration clock signal pin adapted to be connected to corresponding configuration clock signal pins of all of the memory devices such that configuration data is transmitted simultaneously from all of the memory devices to the programmable device.

18 more elements

Dependencies are inferred from the claim text.

Configuring FPGAs and the like using one or more serial memory devices

Life of this patent

Configuring FPGAs and the like using one or more serial memory devices

Life of this patent

Abstract

Claims40