Variable impedance output buffer
AssigneeFreescale Semiconductor, Inc.
InventorsKase Kiyoshi, May Len, Dzung T. Tran
Life of this patent
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Abstract
An output buffer circuit (10, 40, 50) includes an output driver transistor (12), a predriver circuit (14, 54), and a bias generator (16, 54). The predriver circuit (14, 54) has an input terminal for receiving an input signal (IN), a first terminal coupled to a power supply voltage terminal, a second terminal, and an output terminal coupled to the control electrode of the transistor (12). The bias generator (16, 54) is coupled to the second terminal of the predriver circuit (14, 54), and provides a bias voltage (VG) to the second terminal of the predriver circuit (14, 54) for controlling the gate voltage of the output driver transistor (12).
Claims16
An output buffer circuit comprising:
- an output driver transistor having a first current electrode coupled to a power supply voltage terminal, a control electrode, and a second current electrode for providing an output signal;
- a predriver circuit having an input terminal for receiving an input signal, a first terminal coupled to the power supply voltage terminal, a second terminal, and an output terminal coupled to the control electrode of the output driver transistor;
- a resistor having a first terminal coupled to the power supply voltage terminal, and a second terminal;
- a first transistor having a first current electrode coupled to the second terminal of the resistor, a control electrode coupled to the second terminal of the predriver circuit, and a second current electrode;
- and
- a second transistor having a first current electrode coupled to the second terminal of the resistor, a control electrode coupled to the second terminal of the predriver circuit, and a second current electrode.
An output buffer circuit comprising:
- an output driver transistor having a first current electrode coupled to a power supply voltage terminal, a control electrode, and a second current electrode for providing an output signal;
- a predriver circuit having an input terminal for receiving an input signal, a first terminal coupled to the power supply voltage terminal, a second terminal, and an output terminal coupled to the control electrode of the output driver transistor;
- and
- a bias generator coupled to the second terminal of the predriver circuit, for providing a bias voltage to the second terminal of the predriver circuit for controlling the gate voltage of the output driver transistor, the bias generator comprising:
- a resistor having a first terminal coupled to the power supply voltage terminal, and a second terminal;
- a first transistor having a first current electrode coupled to the second terminal of the resistor, a control electrode coupled to the output terminal of the predriver circuit, and a second current electrode, wherein the first transistor is a substantially scaled replica of the output driver transistor;
- and
- a second transistor having a first current electrode coupled to the second terminal of the resistor, a control electrode coupled to the output terminal of the predriver circuit, and a second current electrode.
Dependencies are inferred from the claim text.