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US 7,095,245 B2Granted
Internal voltage reference for memory interface
AssigneeIntel Corporation
InventorsJohn F. Zumkehr, James E. Chandler, Ray I. Chiang
Life of this patent
Estimating the term…
Abstract
Embodiments of the invention include a memory controller to interface to memory. In one embodiment, the memory controller includes a pull-up calibration terminal to couple to an external pull-up resistor, a pull-down calibration terminal to couple to an external pull-down resistor, a voltage reference node, a first switch coupled between the pull-up calibration terminal and the voltage reference node, and a second switch coupled between the pull-down calibration terminal and the voltage reference node. The first switch and the second switch may be selectively closed to generate an internal voltage reference on the voltage reference node in a normal mode that may be used for comparison with an input signal to receive data.
Claims38
An integrated circuit to interface to memory, the integrated circuit comprising:
- a first off chip driver calibration terminal to couple to an external pull-up resistor;
- a first tristate driver having an output coupled to the first off chip driver calibration terminal for pull-up calibration of pull-up transistors;
- a second off chip driver calibration terminal to couple to an external pull-down resistor;
- a second tristate driver having an output coupled to the second off chip driver calibration terminal for pull-down calibration of pull-down transistors;
- a first switch coupled between the first off chip driver calibration terminal and a voltage reference node;
- and
- a second switch coupled between the second off chip driver calibration terminal and the voltage reference node.
4 more elements
An integrated circuit to interface to memory, the integrated circuit comprising:
- a first off chip driver calibration terminal to couple to an external pull-up resistor;
- a second off chip driver calibration terminal to couple to an external pull-down resistor;
- a first switch coupled between the first off chip driver calibration terminal and a voltage reference node;
- a second switch coupled between the second off chip driver calibration terminal and the voltage reference node;
- and
- a plurality of input receivers each having a first input coupled to the voltage reference node and a second input coupled to a respective data terminal of a plurality of data terminals.
3 more elements
An integrated circuit to interface to memory, the integrated circuit comprising:
- a first off chip driver calibration terminal to couple to an external pull-up resistor;
- a first tristate driver having an output coupled to the first off chip driver calibration terminal for pull-up calibration of pull-up transistors;
- a second off chip driver calibration terminal to couple to an external pull-down resistor;
- a second tristate driver having an output coupled to the second off chip driver calibration terminal for pull-down calibration of pull-down transistors;
- a first switch coupled between the first off chip driver calibration terminal and a voltage reference node;
- a second switch coupled between the second off chip driver calibration terminal and the voltage reference node;
- and
- a switch controller having a mode input, a first control output coupled to a control input of the first switch, and a second control output coupled to a control input of the second switch, the switch controller to control the opening and closing of the first switch and the second switch in response to the mode input.
5 more elements
A method in an integrated circuit for interfacing to a memory, the method comprising:
- if in an off-chip driver calibration mode for a pull-up, then
- selecting a pull-up calibration terminal to be coupled to a voltage reference node to provide a pull-up calibration voltage thereon, and
- calibrating a pull-up of an off chip driver;
- if in an off-chip driver calibration mode for a pull-down, then
- selecting a pull-down calibration terminal to be coupled to the voltage reference node to provide a pull-down calibration voltage thereon, and
- calibrating a pull-down of the off chip driver;
- and,
- if in a normal mode to receive data, then
- selecting the pull-up calibration terminal and the pull-down calibration terminal to be coupled to the voltage reference node to provide a reference voltage thereon, and
- receiving data from a data terminal.
7 more elements
A system comprising:
- a processor for executing instructions and processing data;
- a double data rate memory device to store data from the processor and to read data to the processor;
- an external pull-up resistor having a first end coupled to a first power supply terminal;
- an external pull-down resistor having a first end coupled to a second power supply terminal;
- and
- a memory controller coupled between the double data rate memory device and the processor, the memory controller including
- a pull-up calibration terminal coupled to a second end of the external pullup resistor,
- a first tristate driver having an output coupled to the pull-up calibration terminal for pull-up calibration of pull-up transistors in the double data rate memory device,
- a pull-down calibration terminal coupled to a second end of the external pull-down resistor,
- a second tristate driver having an output coupled to the pull-down calibration terminal for pull-down calibration of pull-down transistors in the double data rate memory device,
- a voltage reference node,
- a first switch having a first switch connection coupled to the pull-up calibration terminal and a second switch connection coupled to the voltage reference node, and
- a second switch having a first switch connection coupledto the pull-down calibration terminal and a second switch connection coupled to the voltage reference node.
10 more elements
A processor for a computer system, the processor including:
- a memory controller to interfade to memory, the memory controller having
- a pull-up calibration terminal to couple to an external pull-up resistor,
- a first tristate driver having an output coupled to the pull-up calibration terminal for pull-up calibration of pull-up transistors in the double data rate memory device,
- a pull-down calibration terminal to couple to an external pull-down resistor,
- a second tristate driver having an output coupled to the pull-down calibration terminal for pull-down calibration of pull-down transistors in the double data rate memory device,
- a voltage reference node,
- a first switch coupled between the pull-up calibration terminal and the voltage reference node,
- a second switch coupled between the pull-down calibration terminal and the voltage reference node, and
- a switch controller having a mode input, a first control output coupled to a control input of the first switch, and a second control output coupled to a control input of the second switch, the switch controller to control the opening and closing of the first switch and the second switch in response to the mode input.
6 more elements
A packaged integrated circuit to interface to memory, the packaged integrated circuit comprising:
- a first off-chip driver calibration terminal to couple to a first external resistor;
- a second off-chip driver calibration terminal to couple to a second external resistor;
- a first plurality of field effect transistors having sources coupled in parallel together to the first off-chip driver calibration terminal and drains coupled in parallel together to a voltage reference node;
- and
- a second plurality of field effect transistors having drains coupled in parallel together to the second off-chip driver calibration terminal and sources coupled in parallel together to the voltage reference node.
2 more elements
Dependencies are inferred from the claim text.