Semiconductor device

A semiconductor assembly comprising:

• a wiring board;
• a semiconductor chip which is mounted on the wiring board and in which a multilayer interconnection is formed on a silicon substrate and includes a dual damascene interconnection formed of copper embedded in an interlayer insulation film with a low relative dielectric constant through a barrier metal film;
• and
• a sealing resin layer which covers at least a device-formed surface of the semiconductor chip,
• wherein, the sealing resin layer meets, in coefficient of linear expansion (α) at room temperature, Young's modulus (E) at room temperature and thickness (h) thereof, a relationship of the following formula (1)
• E<0.891/{(α−αs)2×h} (1)
• where
• E represents the Young's modulus (GPa) of the sealing resin at room temperature;
• α represents the coefficient of linear expansion (ppm) of the sealing resin at room temperature;
• αs represents the coefficient of linear expansion (3.5 ppm) of the silicon substrate;
• and
• h represents the thickness (m) of the sealing resin on the device-formed surface of the semiconductor chip.

A semiconductor assembly according to claim 12, wherein, the sealing resin layer meets, in coefficient of linear expansion (α) at room temperature, Young's modulus (E) at room temperature and thickness (h) thereof, a relationship of the following formula (4)

• E<0.792/{(α−αs)2×h} (4)
• where
• E represents the Young's modulus (GPa) of the sealing resin at room temperature;
• α represents the coefficient of linear expansion (ppm) of the sealing resin at room temperature;
• αs represents the coefficient of linear expansion (3.5 ppm) of the silicon substrate;
• and
• h represents the thickness (m) of the sealing resin on the device-formed surface of the semiconductor chip.

A semiconductor device comprising:

• a semiconductor chip in which a multilayer interconnection structure having an interlayer insulation film with a low relative dielectric constant is formed on a silicon substrate;
• and
• a sealing resin layer which coats the semiconductor chip, and comprising a composition including flexible epoxy resin and bisphenol epoxy resin mixed at mixture ratios by weight of 20:80 to 70:30,
• wherein, the sealing resin layer meets, in coefficient of linear expansion (β) at room temperature, Young's modulus (E) at room temperature and thickness (b) thereof, a relationship of the following formula (1)
• E>0.891/{(β−βs)2×h} (1)
• where
• E represents the Young's modulus (GPa) of the sealing resin at room temperature;
• βrepresents the coefficient of linear expansion (ppm) of the sealing resin at room temperature;
• βs represents the coefficient of linear expansion (3.5 ppm) of the silicon substrate;
• and
• h represents the thickness (m) of the sealing resin on the device-formed surface of the semiconductor chip.

A semiconductor device comprising:

• a semiconductor chip in which a multilayer interconnection structure having an interlayer insulation film with a low relative dielectric constant is formed on a silicon substrate;
• and
• a sealing resin layer which coats the semiconductor chip, composition in which a granular filler is mixed into silicone rubber-based resin,
• wherein, the sealing resin layer meets, in coefficient of linear expansion (β) at room temperature, Young's modulus (E) at room temperature and thickness (h) thereof, a relationship of the following formula (1)
• E>0.891/{(β−βs)2×h{ (1)
• where
• E represents the Young's modulus (GPa) of the sealing resin at room temperature;
• βrepresents the coefficient of linear expansion (ppm) of the sealing resin at room temperature;
• βs represents the coefficient of linear expansion (3.5 ppm) of the silicon substrate;
• and
• h represents the thickness (m) of the sealing resin on the device-formed surface of the semiconductor chip.