Pad rearrangement substrate
AssigneeKabushiki Kaisha Toshiba
InventorsMinori Kajimoto, Osamu Ikeda, Masaki Momodomi
Life of this patent
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Abstract
A pad rearrangement substrate includes an internal terminal provided on a mounting plane of a dielectric substrate, an external terminal provided on the external terminal plane of the dielectric substrate, an internal wiring pattern connecting the external terminal to the internal terminal, an antenna pattern provided at a corner portion of the external terminal plane of the dielectric substrate, an external terminal provided on the external terminal plane of the dielectric substrate, and a dielectric layer. The antenna pattern is connected to the dummy external terminal. The dielectric layer coats the external terminal plane of the dielectric substrate except the external terminal and the dummy external terminal.
Claims16
A pad rearrangement substrate comprising:
- a dielectric substrate having a mounting plane configured to be mounted with a semiconductor chip, and an external terminal plane;
- an internal terminal provided on the mounting plane of the dielectric substrate, and configured to be connected to a bonding pad of the semiconductor chip;
- an external terminal provided on the external terminal plane of the dielectric substrate, and configured to rearrange the bonding pad of the semiconductor chip to be connected to a circuit board;
- an internal wiring pattern provided in the dielectric substrate, and connecting the external terminal to the internal terminal;
- an antenna pattern provided at a corner portion of the external terminal plane of the dielectric substrate and configured to be grounded;
- a dummy external terminal provided on the external terminal plane of the dielectric substrate and connected to the antenna pattern;
- and
- a dielectric layer coating the external terminal plane of the dielectric substrate except the external terminal and the dummy external terminal.
Dependencies are inferred from the claim text.