US 7,095,081 B2Granted

Semiconductor device and manufacturing method thereof

AssigneeKabushiki Kaisha Toshiba

InventorsTakashi Yamada, Hajime Nagano, Takeshi Hamamoto

Life of this patent

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Abstract

A semiconductor device includes a substrate having first to fourth regions, a first insulating film formed on the substrate in the first region, a first epitaxial layer formed on the substrate in the second region and having an upper surface higher than an upper surface of the first insulating film, a first semiconductor layer formed on the first insulating film with a space provided with respect to the first epitaxial layer and having an upper surface set at substantially the same height as the upper surface of the first epitaxial layer, and an element isolation insulating film formed in the space and having an upper surface set at substantially the same height as the upper surface of the first epitaxial layer and the upper surface of the first semiconductor layer.

Claims3

Dependent claims

A semiconductor device comprising:

a substrate having first and second regions,
a first insulating film formed on the substrate in the first region,
an epitaxial layer formed on the substrate in the second region with a first space provided with respect to the first insulating film and having an upper surface higher than an upper surface of the first insulating film,
a semiconductor layer having a first portion formed on the first insulating film and a second portion which projects from a side surface of the first insulating film on the epitaxial layer side and formed with a second space provided with respect to the epitaxial layer, upper surfaces of the first and second portions being set at substantially the same height as the upper surface of the epitaxial layer, and
an element isolation insulating film formed in the first and second spaces and having an upper surface set at substantially the same height as the upper surface of the epitaxial layer and the upper surfaces of the first and second portions.

2 more elements

Dependencies are inferred from the claim text.

Facts

Application: 11/331,316Filed 13 Jan 2006 · division
Priority: JP 2003-20931128 Aug 2003
Published: US 2006/0118873 A18 Jun 2006
Granted: 22 Aug 2006
Term ends: Not estimatedThe source records don’t support an estimate.

Classification18 codes

H10D 84/038
Using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology: using silicon technology, e.g. SiGe
H10B 41/40
Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates: characterised by the peripheral circuit region
H10B 41/43
Simultaneous manufacture of periphery and memory cells: comprising only one type of peripheral transistor
H10D 30/711
Insulated-gate field-effect transistors [IGFET]: having floating bodies

Family

Application10/699,676Parent of this division · filed 4 Nov 2003
US 2006/0118873 A1Pre-grant publication · published 8 Jun 2006
US 2005/0045951 A1Published application
US 7,049,661 B2Related patent
US 7,095,081 B2This patent

From the US filing history. Foreign family members aren’t listed.