Etch aided by electrically shorting upper and lower sidewall portions during the formation of a semiconductor device

A method used in the fabrication of a semiconductor device comprising:

• providing a dielectric layer at a location over a conductive feature;
• placing the dielectric layer and the conductive feature into a chamber;
• performing an etch which only partially etches into the dielectric layer over the conductive feature to form a sidewall in the dielectric layer, the sidewall having upper and lower portions, then stopping the etch;
• subsequent to stopping the etch, flowing a gas into the chamber to electrically short the upper portion of the sidewall to the lower portion of the sidewall, then stopping the flow of the gas into the chamber;
• subsequent stopping the flow of gas into the chamber, further etching into the dielectric layer to expose the conductive feature and to form an opening in the dielectric layer;
• and
• forming a conductive plug within the opening which contacts the conductive feature and fills the opening formed in the dielectric layer.

A method used in the fabrication of a semiconductor device comprising:

• providing a dielectric layer;
• providing a patterned photoresist layer having an opening therein which exposes the dielectric layer;
• only partially etching into the dielectric layer to form an opening therein defined by first and second cross-sectional dielectric sidewalls, the dielectric sidewalls each having an upper region and a lower region;
• forming a conformal conductive layer over the upper and lower regions of the first and second dielectric sidewalls;
• subsequent to forming the conductive layer, further etching the dielectric layer to extend the opening into the dielectric layer;
• and
• forming a conductive plug within the opening in the dielectric layer which fills the opening in the dielectric layer.

A method used in the fabrication of a semiconductor device comprising:

• providing a semiconductor substrate assembly comprising at least one dielectric layer formed thereover;
• performing a first etch which only partially etching into the dielectric layer to form at least one sidewall, wherein the etching results in regions of positive and negative electrical potential along the sidewall, then stopping the first etch;
• subsequent to stopping the first etch, electrically shorting the regions of positive and negative electrical potential to each other and dissipating the electrical potential;
• subsequent to electrically shorting the regions of positive and negative electrical potential to each other, performing a second etch into the dielectric layer to form an opening in the dielectric layer;
• and
• forming a conductive plug within the opening in the dielectric layer which fills the opening.

A method used in the fabrication of a semiconductor device comprising:

• providing a semiconductor substrate assembly having a region to be exposed;
• providing a dielectric layer over the semiconductor substrate assembly;
• only partially etching a portion of the dielectric layer to form an opening therein defined by at least one cross-sectional sidewall and a bottom;
• forming a blanket conductive layer comprising at least one of titanium, conductively-doped polysilicon, and titanium nitride within the opening on the bottom and the at least one sidewall to electrically short an upper region of the at least one sidewall with a lower region of the at least one sidewall;
• anisotropically etching the conductive layer to remove the conductive layer from the bottom and leaving the conductive layer over the at least one sidewall;
• subsequent to anisotropically etching the conductive layer, further etching the dielectric layer at the bottom of the opening to form a second sidewall in the dielectric layer below a level of the conductive layer;
• and
• forming a conductive plug within the opening which fills the opening.