Semiconductor device having MOS varactor and methods for fabricating the same
AssigneeSamsung Electronics Co., Ltd.
InventorsKong-Soo Cheong, Ki-Seog Youn, Kyung-Soo Kim
Life of this patent
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Abstract
In a method for manufacturing a semiconductor device, a gate electrode is formed in a first region. A silicide blocking layer is patterned such that a first gate spacer is formed on sidewalls of the gate electrode, and a silicide blocking layer pattern is formed in a second region. A lightly doped source/drain region is formed on surface of the first region. A second gate spacer is formed on sidewalls of the first gate spacer. A heavily doped source/drain region is formed on the surface of the first region. A silicide layer is formed on the gate electrode and the heavily doped source/drain region in the first region.
Claims20
A method for manufacturing a semiconductor device, comprising:
- forming a gate electrode on a first region of a semiconductor substrate;
- forming a silicide blocking layer on the substrate and the gate electrode;
- partially removing the silicide blocking layer to form a first gate spacer on sidewalls of the gate electrode on the first region and a silicide blocking layer pattern on a second region;
- implanting dopants lightly into the substrate using the silicide blocking layer, the gate electrode, and the first gate spacer as a first implantation mask to form a lightly doped source/drain region on the first region;
- forming a second gate spacer on sidewalls of the first gate spacer;
- implanting dopants heavily into the substrate using the silicide blocking layer, the gate electrode, the first gate spacer, and the second gate spacer as a second implantation mask to form a heavily doped source/drain region on the first region;
- and
- forming a silicide layer on the gate electrode and the heavily doped source/drain region in the first region.
A method for manufacturing a semiconductor device, comprising:
- forming a gate electrode in a transistor region of a semiconductor substrate, the substrate being divided into the transistor region and a resistor region;
- forming a silicide blocking layer on the substrate and the gate electrode;
- partially removing the silicide blocking layer such that a first gate spacer is formed on sidewalls of the gate electrode on the transistor region and a silicide blocking layer formed on the resistor region;
- implanting dopants lightly into the surface of the substrate using the silicide blocking layer, the gate electrode, and the first gate spacer as a first implantation mask to form a lightly doped source/drain region on the surface of the transistor region;
- forming a second gate spacer on sidewalls of the first gate spacer;
- implanting dopants heavily into the surface of the substrate using the silicide blocking layer, the gate electrode, the first gate spacer, and the second gate spacer as a second implantation mask to form a heavily doped source/drain region on the surface of the transistor region;
- and
- forming a silicide layer on the gate electrode and the heavily doped source/drain region in the transistor region.
A method of manufacturing a semiconductor device, comprising:
- forming a gate electrode in a transistor region of a semiconductor substrate, the substrate being divided into the transistor region and a resistor region;
- forming a first gate spacer on sidewalls of the gate electrode;
- implanting dopants lightly into the surface of the substrate using the gate electrode and the first gate spacer as a first implantation mask to form a lightly doped source/drain region;
- forming a silicide blocking layer on the substrate and the lightly doped source/drain region;
- partially removing the silicidation blocking layer such that a second gate spacer is formed on sidewalls of the first gate spacer in the transistor region and a silicide blocking layer pattern is formed in the resistor region;
- implanting dopants heavily into the surface of the substrate using the silicide blocking layer, the gate electrode, the first gate spacer, and the second gate spacer as a second implantation mask to form a heavily doped source/drain region on the surface of the transistor region;
- and
- forming a silicide layer on the gate electrode and the heavily doped source/drain region in the transistor region.
Dependencies are inferred from the claim text.