Semiconductor device and method of manufacturing the same

A method of manufacturing a semiconductor device, comprising:

• forming a first gate insulating film for a high voltage transistor on a semiconductor substrate;
• forming a second gate insulating film for a low voltage transistor on the semiconductor substrate, said second gate insulating film being thinner than said first gate insulating film;
• forming a gate of a first high voltage transistor and a gate of a second high voltage transistor on said first gate insulating film by stacking conductive materials to form a stacked gate structure followed by selectively patterning the stacked gate structure;
• forming a gate of a first low voltage transistor and a gate of a second low voltage transistor on said second gate insulating film by depositing a conductive material followed by selectively patterning the conductive material;
• introducing an impurity of a first conductivity type with a low concentration into the semiconductor substrate using gates of said second high voltage transistor and said second low voltage transistor as masks, and introducing an impurity of a second conductivity type with a low concentration into the semiconductor substrate using gates of said first high voltage transistor and said first low voltage transistor as masks;
• depositing a first side wall material over the gates of the transistors;
• forming a first side wall on side surfaces of said gates of the transistors by selectively etching said first side wall material by means of an anisotropic etching;
• introducing an impurity of the second conductivity type with a high concentration into the semiconductor substrate using said side walls of said first high voltage transistor and said first low voltage transistor as masks;
• depositing a second side wall material and a third side wall material differing from said second side wall material over said first side walls and gates of the transistors;
• forming a third side wall on the side surface of said second side wall by selectively etching said third side wall material by means of an anisotropic etching using the second side wall material as an etching stopper;
• introducing an impurity of said first conductivity type with a high concentration into the semiconductor substrate using said third side walls of said second high voltage transistor and said second low voltage transistor as masks;
• depositing an interlayer insulating film on the entire surface of said semiconductor substrate;
• and
• selectively forming contact holes in said interlayer insulating film.

A method of manufacturing a semiconductor device, comprising:

• forming an element isolating region in a semiconductor substrate;
• forming a tunnel oxide film for a memory cell, a floating gate material and an inter-electrode insulating film;
• forming a first gate insulating film for a high voltage transistor on said semiconductor substrate;
• forming a second gate insulating film for a low voltage transistor on said semiconductor substrate, said second gate insulating film being thinner than said first gate insulating film;
• forming a gate of the memory cell by depositing a conductive material for a control gate followed by selectively patterning successively said control gate material, said inter-electrode insulating film, and said floating gate material;
• selectively patterning a conductive material to form a gate gate of a first high voltage transistor and a gate of a second high voltage transistor on said first gate insulating film, and to form a gate of a first low voltage transistor and a gate of a second low voltage transistor on said second gate insulating film;
• introducing an impurity of a second conductivity type with a high concentration into the semiconductor substrate using the gate of the memory cell, introducing an impurity of the second conductivity type with a low concentration into the semiconductor substrate using the gates of said first high voltage transistor and said first low voltage transistor as masks, and introducing an impurity of a first conductivity type with a low concentration into the semiconductor substrate using gates of said second high voltage transistor and said second low voltage transistor as masks;
• depositing a first side wall material over the gates of the transistors;
• forming a first side wall on side surfaces of said gates of transistors by selectively etching the first side wall material by an anisotropic etching;
• introducing an impurity of the second conductivity type with a high concentration into the semiconductor substrate using said first side walls of said first high voltage transistor and said first low voltage transistor as masks;
• depositing a second side wall material and a third side wall material differing from said second side wall material over said first side walls and gates of the transistors;
• forming a third side wall on the side surface of said second side wall by selectively etching said third side wall material by an anisotropic etching using the second side wall material as an etching stopper;
• introducing an impurity of the first conductivity type with a high concentration into said semiconductor substrate using said third side walls of said second high voltage transistor and said second low voltage transistor as masks;
• removing said third side wall;
• depositing an interlayer insulating film on the entire surface of said semiconductor substrate;
• selectively forming contact holes in said interlayer insulating film;
• forming a metal wiring;
• and
• forming an insulating film on said metal wiring.

A method of manufacturing a semiconductor device, comprising:

• forming an element isolating region in a semiconductor substrate;
• forming a first gate insulating film for a high voltage transistor on said semiconductor substrate;
• forming a second gate insulating film for a low voltage transistor on the semiconductor substrate, said second gate insulating film being thinner than said first gate insulating film;
• forming gates of first and second high voltage transistors on said first pate insulating film and gates of first and second low voltage transistor on said second gate insulating film by stacking a conductive material layer followed by pattering said conductive material layer by an etching;
• introducing an impurity of a second conductivity type with a low conductive into the semiconductor substrate using gates of said first high voltage transistor and said first low voltage transistor as masks;
• depositing a first side wall material over the gates of the transistors;
• forming a first side wall on side surfaces of said gates of the transistors by selectively etching said first side wall material by an anisotropic etching;
• introducing an impurity of a first conductivity type with a low concentration into the semiconductor substrate with said first side walls of the gates of said second high voltage transistor and said second low voltage transistor using as masks;
• introducing an impurity of the second conductivity type with a high concentration into the semiconductor substrate using said side walls of said first high voltage transistor and said first low voltage transistor as masks;
• depositing a second side wall material and a third side wall material differing from said second side wall material over said first side walls and gates of the transistors;
• forming a third side wall on the side surface of said second side wall material by selectively etching said third side wall material by an anisotropic etching using the second side wall material as an etching stopper;
• introducing an impurity of the first conductivity type with a high concentration into the semiconductor substrate that in the impurity diffusion layer of the first conductivity type using said third side walls of said second high voltage transistor and said second low voltage transistor as masks;
• removing the third side wall;
• depositing an interlayer insulating film on the entire substrate;
• and
• selectively forming contact holes in said interlayer insulating film.

A method of manufacturing a semiconductor device, comprising:

• introducing an impurity of a first conductivity type into a semiconductor substrate;
• forming a tunnel oxide film and a floating gate material in a memory cell region on the semiconductor substrate;
• forming a first gate insulating film for a high voltage transistor in a part of a peripheral circuit region on the semiconductor substrate;
• forming a second gate insulating film for a low voltage transistor in another part of the peripheral circuit region on the semiconductor substrate, said second gate insulating film being thinner than said first gate insulating film;
• forming an inter-electrode insulating film on the floating gate material;
• forming a gate of a memory cell by depositing conductive material for a control gate followed by selectively patterning the control gate material, said inter-electrode insulating film, and said floating gate material successively;
• selectively patterning a conductive material to form a gate of a first high voltage transistor and a gate of a second high voltage transistor on said first gate insulating film and a gate of a first low voltage transistor and a gate of a second low voltage transistor on said second gate insulating film in a peripheral circuit region;
• introducing an impurity of a second conductivity type with a high concentration into the semiconductor substrate using the gate of the memory cell, and introducing the impurity of the second conductivity type into the semiconductor substrate using the gates of said first high voltage transistor and said first low voltage transistor as masks;
• depositing a first side wall material over the gates of the transistors;
• forming a first side wall on side surface of said gates of transistors by selectively etching said first side wall material by an anisotropic etching;
• introducing an impurity of a first conductivity type with a low concentration into the semiconductor substrate using said first side walls of the gates of said second high voltage transistor and said second low voltage transistor as masks;
• introducing an impurity of the second conductivity type with a high concentration into the semiconductor substrate using said side walls of said first high voltage transistor and said first low voltage transistor as masks;
• depositing a second side wall material and a third side wall material differing from said second side wall material over said first side walls and gates of the transistors;
• forming a third side wall on the side surface of the second side wall material by selectively etching said third side wall material by an anisotropic etching using the second side wall material as an etching stopper;
• introducing an impurity of the first conductivity type with a high concentration into the semiconductor substrate using said third side walls of said second high voltage transistor and said second low voltage transistor as masks;
• removing said third side wall;
• depositing an interlayer insulating film on the entire surface of the substrate;
• selectively forming contact holes in said interlayer insulating film;
• forming at least a single metal wiring;
• and
• forming an insulating film on said metal wiring.