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US 7,094,649 B2Granted
Method for forming multi-level mask ROM cell and NAND multi-level mask ROM
AssigneeSolid State System Co., Ltd.
InventorsChien-Hsing Lee, Chin-Hsi Lin, Jhyy-Cheng Liou
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Abstract
The present invention relates to a multi-level read only memory cell that can store two bits and the fabrication method thereof. The multi-level ROM cell has the storage capacity of two bits and the resultant NAND type ROM memory array can provide four logic states of two bits, thus increasing the data storage capacity.
Claims30
A method for forming a mask read only memory structure, comprising:
- providing a substrate having a memory region and a periphery region;
- performing a threshold voltage implantation to adjust a threshold voltage of the memory region;
- forming a plurality of gate structures on the substrate, wherein the gate structure includes a gate oxide layer on the substrate and a gate conductive layer on the gate oxide layer;
- forming spacers on sidewalls of the gate structures;
- forming a plurality of source/drain regions in the substrate along both sides of the spacers;
- applying a first patterned photoresist layer with a first code pattern to the substrate and then performing a first code implantation to the memory region using the first patterned photoresist layer with the first code pattern as a mask;
- applying a second patterned photoresist layer with a second code pattern to the substrate and then performing a second code implantation to the memory region using the second patterned photoresist layer with the second code pattern as a mask;
- forming an interlayer over the substrate;
- and
- forming at least a contact plug in the interlayer.
7 more elements
A method for forming a mask read only memory structure, comprising:
- providing a substrate having a memory region and a periphery region;
- performing a threshold voltage implantation to adjust a threshold voltage of the memory region;
- forming a plurality of word lines on the substrate;
- forming first spacers on sidewalls of the word lines;
- forming a plurality of source/drain regions in the substrate along both sides of the first spacers;
- performing a first code implantation to the memory region using a first patterned photoresist layer with a first code pattern as a mask, so as to obtain memory cells with a first threshold voltage range and memory cells with a second threshold voltage range;
- and
- performing a second code implantation to the memory region using a second patterned photoresist layer with a second code pattern as a mask, so as to obtain memory cells with a third threshold voltage range and memory cells with a fourth threshold voltage range, in addition to the memory cells with the first threshold voltage and with the second threshold voltage range.
5 more elements
Dependencies are inferred from the claim text.