US 7,094,646 B2Granted

Flash memory device having a split gate and method of manufacturing the same

AssigneeSamsung Electronics Co., Ltd.

InventorsEui-youl Ryu, Chul-soon Kwon, Jin-woo Kim, Yong-hee Kim, Dai-geun Kim, Joo-chan Kim

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Abstract

A flash memory device having a split gate that can prevent an active region and a floating gate electrode from being misaligned, and a method of manufacturing the same, includes sequentially stacking a gate oxide layer and a floating gate conductive layer on a semiconductor substrate, forming an isolation layer in a predetermined region of the semiconductor substrate where the floating gate conductive layer is formed, and defining an active region. Then, a local oxide layer is formed by oxidizing a predetermined part of the floating gate conductive layer on the active region. A floating gate electrode structure is formed by patterning the floating gate conductive layer using the local oxide layer.

Claims22

Dependent claims

A method of manufacturing a flash memory device having a split gate, comprising:

sequentially stacking a gate oxide layer and a floating gate conductive layer on a semiconductor substrate;
forming an isolation layer in a predetermined region of the semiconductor substrate using a mask when the floating gate conductive layer is formed, thereby defining an active region;
etching the mask to expose the floating gate conductive layer corresponding to a prearranged floating gate pattern;
forming a local oxide layer by oxidizing the exposed floating gate conductive layer in the active region using the mask;
forming a floating gate structure by patterning the floating gate conductive layer using the local oxide layer as a mask,
sequentially stacking an inter-gate electrode insulating layer, a control gate conductive layer and a hard mask layer on a resultant structure on the semiconductor substrate;
etching predetermined parts of the hard mask layer, control gate conductive layer, inter-gate electrode insulating layer and the local oxide layer to expose a predetermined part of the floating gate structure;
forming an insulating spacer on a sidewall of the hard mask layer, a sidewall of the control gate conductive layer and a sidewall of the local oxide layer;
and
etching the floating gate structure using the insulating spacer as a mask, thereby defining a floating gate electrode and a source region.

7 more elements

A method of manufacturing a flash memory device having a split gate, comprising:

sequentially stacking a gate oxide layer and a floating gate conductive layer on a semiconductor substrate;
forming an isolation layer in a predetermined region of the semiconductor substrate when the floating gate conductive layer is formed, thereby defining an active region;
forming a local oxide layer by oxidizing a predetermined part of the floating gate conductive layer in the active region;
forming a floating gate structure by patterning the floating gate conductive layer using the local oxide layer as a mask;
sequentially stacking an inter-gate electrode insulating layer, a control gate conductive layer and a hard mask layer on a resultant structure on the semiconductor substrate;
etching predetermined parts of the hard mask layer, control gate conductive layer, inter-gate electrode insulating layer and the local oxide layer to expose a predetermined part of the floating gate structure;
forming an insulating spacer on a sidewall of the hard mask layer, a sidewall of the control gate conductive layer and a sidewall of the local oxide layer;
and
etching the floating gate structure using the insulating spacer as a mask, thereby defining a floating gate electrode and a source region.

6 more elements

A method of manufacturing a flash memory device having a split gate, comprising:

sequentially stacking a gate oxide layer and a floating gate conductive layer on a semiconductor substrate;
forming an isolation layer in a predetermined region of the semiconductor substrate when the floating gate conductive layer is formed, thereby defining an active region;
forming a local oxide layer by oxidizing a predetermined part of the floating gate conductive layer in the active region;
forming a floating gate structure by patterning the floating gate conductive layer using the local oxide layer as a mask;
forming a control gate structure including an inter-gate electrode insulating layer, a control gate conductive layer and a hard mask layer on a resultant structure of the semiconductor substrate, the control gate structure exposing a predetermined part of the floating gate structure;
etching the local oxide layer using the control gate structure as a mask;
forming an insulating spacer on a sidewall of the control gate structure and a sidewall of the local oxide layer;
etching the exposed floating gate structure and the isolation layer using the insulating spacer as a mask, thereby defining a pair of floating gate electrodes and a trench for a path;
forming a source region in the active region exposed between the pair of floating gate electrodes and a source path in a lower part of the trench for the path;
forming a control gate electrode by etching a predetermined part of the control gate structure;
and
forming a drain region in the active region on one side of the control gate electrode.

9 more elements

A method of manufacturing a flash memory device having a split gate, comprising:

sequentially stacking a gate oxide layer and a floating gate conductive layer on a semiconductor substrate;
forming an isolation layer in a predetermined region of the semiconductor substrate using a mask when the floating gate conductive layer is formed, thereby defining an active region;
etching the mask to expose the floating gate conductive layer corresponding to a prearranged floating gate pattern;
forming a local oxide layer by oxidizing the exposed floating gate conductive layer in the active region using the mask;
forming a floating gate structure by patterning the floating gate conductive layer using the local oxide layer as a mask
forming a control gate structure including an inter-gate electrode insulating layer, a control gate conductive layer and a hard mask layer on a resultant structure of the semiconductor substrate, the control gate structure exposing a predetermined part of the floating gate structure;
etching the local oxide layer using the control gate structure as a mask;
forming an insulating spacer on a sidewall of the control gate structure and a sidewall of the local oxide layer;
etching the exposed floating gate structure and the isolation layer using the insulating spacer as a mask, thereby defining a pair of floating gate electrodes and a trench for a path;
forming a source region in the active region exposed between the pair of floating gate electrodes and a source path in a lower part of the trench for the path;
forming a control gate electrode by etching a predetermined part of the control gate structure;
and
forming a drain region in the active region on one side of the control gate electrode.

10 more elements

Dependencies are inferred from the claim text.

Facts

Application: 11/119,801Filed 3 May 2005
Priority: KR 10-2004-00316716 May 2004
Published: US 2005/0250282 A110 Nov 2005
Granted: 22 Aug 2006
Term ends: Not estimatedThe source records don’t support an estimate.

Classification6 codes

H10D 30/681
Floating-gate IGFETs: having only two programming levels
H10B 41/30
Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates: characterised by the memory core region
H10B 69/00
Erasable-and-programmable rom [eprom] devices not provided for in groups h10b41/00 - h10b63/00
H10D 30/6891
Floating-gate IGFETs: characterised by the shapes, relative sizes or dispositions of the floating gate electrode