Method for controlling accuracy and repeatability of an etch process
AssigneeApplied Materials, Inc.
InventorsDavid Mui, Wei Liu, Hiroki Sasano
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Abstract
Embodiments of the invention generally relate to a method for etching in a processing platform (e.g. a cluster tool) wherein robust pre-etch and post-etch data may be obtained in-situ. The method includes the steps of obtaining pre-etched critical dimension (CD) measurements of a feature on a substrate, etching the feature; treating the etched substrate to reduce and/or remove sidewall polymers deposited on the feature during etching, and obtaining post-etched CD measurements. The CD measurements may be utilized to adjust the etch process to improved the accuracy and repeatability of device fabrication.
Claims20
A method for controlling accuracy and repeatability of an etch process, comprising:
- (a) providing a batch of substrates, each substrate having a patterned mask formed on a film stack comprising at least one material layer;
- (b) measuring dimensions of elements of the patterned mask on at least one substrate of the batch of substrates;
- (c) trimming the patterned mask on the at least one substrate using a process recipe based on the measurements performed at step (b), then;
- (d) etching the at least one material layer on the at least one substrate;
- (e) measuring a thickness of post-etch residue and at least one of compacting or removing at least a portion of the post-etch residue formed on sidewalls of the etched structures based on the thickness of the post-etch residue;
- (f) measuring dimensions of etched structures formed on the at least one substrate during step (d);
- and
- (g) adjusting the process recipe of step (c) or/and the process recipe of step (d);
- based on the measurements performed at step (f).
A method for controlling accuracy and repeatability during formation of a gate structure of a field effect transistor, comprising:
- (a) providing a batch of substrates, each substrate having a patterned mask formed on a gate electrode layer of the gate structure;
- (b) measuring dimensions of elements of the patterned mask on at least one substrate of the batch of substrates;
- (c) trimming the patterned mask on the at least one substrate using a process recipe based on the measurements performed at step (b), then;
- (d) etching the gate electrode layer on the at least one substrate;
- (e) measuring a thickness of post-etch residue and at least one of compacting or removing at least the portion of post-etch residue formed on sidewalls of the etched structures based on the thickness of the post-etch residue;
- (f) measuring dimensions of etched gate electrode structures formed on the at least one substrate during step (d);
- and
- (g) adjusting the process recipe of step (c) or/and the process recipe of step (d) based on the measurements performed at step (f).
Dependencies are inferred from the claim text.