Rejection of power supply variations for gain error cancellation in pulse-width-modulated motor controllers

A pulse-width-modulation driver circuit, comprising:

• a first driver pair comprising first and second transistors having conduction paths connected in series between a power supply voltage and a ground voltage, each of the first and second transistors having a control terminal;
• pulse-width-modulation circuitry, for generating a first pulse-width-modulated signal responsive to a comparison of an error signal with a ramp clock signal;
• a first pulse-width-modulation driver, having an input coupled to receive the first pulse-width modulated signal and having outputs coupled to the control terminals of the first and second transistors;
• a ramp clock generator, for generating the ramp clock signal that varies periodically between the high limit and the low limit, the ramp clock generator comprising circuitry for changing the high and low limits responsive to variations in the power supply voltage;
• and
• circuitry for changing the slope of the ramp clock signal responsive to variations in the power supply voltage.

A pulse-width-modulation driver circuit, comprising:

• a first driver pair comprising first and second transistors having conduction paths connected in series between a power supply voltage and a ground voltage, each of the first and second transistors having a control terminal;
• pulse-width-modulation circuitry, for generating a first pulse-width-modulated signal responsive to a comparison of an error signal with a ramp clock signal;
• a first pulse-width-modulation driver, having an input coupled to receive the first pulse-width modulated signal and having outputs coupled to the control terminals of the first and second transistors;
• and
• a ramp clock generator, for generating the ramp clock signal that varies periodically between the high limit and the low limit, the ramp clock generator comprising circuitry for changing the high and low limits responsive to variations in the power supply voltage,
• wherein the ramp clock generator comprises:
• a timing capacitor;
• a charging circuit, for periodically charging the timing capacitor;
• a discharging circuit, for periodically discharging the timing capacitor;
• a level detector, for detecting a voltage at the timing capacitor, for controlling the charging circuit to charge the timing capacitor responsive to the detected voltage reaching the low limit, and for controlling the discharging circuit to discharge the timing capacitor responsive to the detected voltage reaching the high limit;
• and
• control circuitry, for measuring the power supply voltage and for communicating the high and low limits to the level detector responsive to the measured power supply voltage.

A method of controlling a pulse-width-modulated drive circuit, comprising:

• generating a ramp clock signal that varies periodically between a high limit and a low limit;
• comparing an error signal to the ramp clock signal;
• generating a first pulse-width-modulated signal at a duty cycle responsive to the comparing of the error signal to the ramp clock signal having variable high and low limits;
• driving control terminals of a first pair of driver transistors responsive to the first pulse-width-modulated signal, the first pair of driver transistors having conduction paths connected in series between a power supply voltage and a reference voltage;
• responsive to the power supply voltage being higher than a nominal value, reducing the duty cycle of the first pulse-width-modulated signal;
• and
• responsive to the power supply voltage being lower than the nominal value, increasing the duty cycle of the first pulse-width-modulated signal.

A method of controlling a pulse-width-modulated drive circuit, comprising:

• generating a ramp clock signal that varies periodically between a high limit and a low limit;
• comparing an error signal to the ramp clock signal;
• generating a first pulse-width-modulated signal at a duty cycle responsive to the comparing of the error signal to the ramp clock signal;
• driving control terminals of a first pair of driver transistors responsive to the first pulse-width-modulated signal, the first pair of driver transistors having conduction paths connected in series between a power supply voltage and a reference voltage;
• responsive to the power supply voltage being higher than a nominal value, reducing the duty cycle of the first pulse-width-modulated signal;
• and
• responsive to the power supply voltage being lower than the nominal value, increasing the duty cycle of the first pulse-width-modulated signal,
• wherein the reducing step comprises:
• increasing the high limit;
• and
• decreasing the low limit.

A disk drive system, comprising:

• a magnetic disk;
• a positioning arm extended over the magnetic disk;
• a data transducer mounted at a distal end of the positioning arm;
• a voice coil motor coupled to a proximal end of the positioning arm, for pivoting the positioning arm;
• a first driver pair comprising first and second transistors having conduction paths connected in series between a power supply voltage and a ground voltage, the voice coil motor coupled to a node at the connection between the conduction paths of the first and second transistors, and each of the first and second transistors having a control terminal;
• pulse-width-modulation circuitry, for generating a first pulse-width-modulated signal responsive to a comparison of an error signal with a ramp clock signal having variable high and low limits;
• a first pulse-width-modulation driver, having an input coupled to receive the first pulse-width modulated signal and having outputs coupled to the control terminals of the first and second transistors;
• and
• a ramp clock generator, for generating a ramp clock signal that varies periodically between the high limit and the low limit, the ramp clock generator comprising circuitry for changing the high and low limits responsive to variations in the power supply voltage.

A disk drive system, comprising:

• a magnetic disk;
• a positioning arm extended over the magnetic disk;
• a data transducer mounted at a distal end of the positioning arm;
• a voice coil motor coupled to a proximal end of the positioning arm, for pivoting the positioning arm;
• a first driver pair comprising first and second transistors having conduction paths connected in series between a power supply voltage and a ground voltage, the voice coil motor coupled to a node at the connection between the conduction paths of the first and second transistors, and each of the first and second transistors having a control terminal;
• pulse-width-modulation circuitry, for generating a first pulse-width-modulated signal responsive to a comparison of an error signal with a ramp clock signal;
• a first pulse-width-modulation driver, having an input coupled to receive the first pulse-width modulated signal and having outputs coupled to the control terminals of the first and second transistors;
• and
• a ramp clock generator, for generating a ramp clock signal that varies periodically between a high limit and a low limit, the ramp clock generator comprising circuitry for changing the high and low limits responsive to variations in the power supply voltage,
• wherein the ramp clock generator further comprises:
• circuitry for changing the slope of the ramp clock signal responsive to variations in the power supply voltage.

A disk drive system, comprising:

• a magnetic disk;
• a positioning arm extended over the magnetic disk;
• a data transducer mounted at a distal end of the positioning arm;
• a voice coil motor coupled to a proximal end of the positioning arm, for pivoting the positioning arm;
• a first driver pair comprising first and second transistors having conduction paths connected in series between a power supply voltage and a ground voltage, the voice coil motor coupled to a node at the connection between the conduction paths of the first and second transistors, and each of the first and second transistors having a control terminal;
• pulse-width-modulation circuitry, for generating a first pulse-width-modulated signal responsive to a comparison of an error signal with a ramp clock signal;
• a first pulse-width-modulation driver, having an input coupled to receive the first pulse-width modulated signal and having outputs coupled to the control terminals of the first and second transistors;
• and
• a ramp clock generator, for generating a ramp clock signal that varies periodically between a high limit and a low limit, the ramp clock generator comprising circuitry for changing the high and low limits responsive to variations in the power supply voltage,
• wherein the ramp clock generator comprises:
• a timing capacitor;
• a charging circuit, for periodically charging the timing capacitor;
• a discharging circuit, for periodically discharging the timing capacitor;
• a level detector, for detecting a voltage at the timing capacitor, for controlling the charging circuit to charge the timing capacitor responsive to the detected voltage reaching the low limit, and for controlling the discharging circuit to discharge the timing capacitor responsive to the detected voltage reaching the high limit;
• and
• control circuitry, for measuring the power supply voltage and for communicating the high and low limits to the level detector responsive to the measured power supply voltage.