Method for optimizing utilization of a double-data-rate-SDRAM memory system
AssigneeSun Microsystems, Inc.
InventorBrian D. Emberling
Life of this patent
Estimating the term…
Abstract
A predictive memory performance optimizing unit for use with an interleaved memory, for example a DDR SDRAM memory, and suitable for use in a computer graphics system, among others, is described. The unit maintains a queue of pending requests for data from the memory, and prioritizes precharging and activating interleaves with pending requests. Interleaves which are in a ready state may be accessed independently of the precharging and activation of non-ready interleaves. The unit utilizes idle cycles occurring between consecutive requests to activate interleaves with pending requests.
Claims22
A system comprising:
- a memory controller;
- a module coupled to the memory controller;
- and
- a buffer coupled to the module configured to receive and store read-requests;
- wherein the module is operable to:
- transmit read-requests from the buffer to the memory controller;
- analyze a current sequence of read-requests stored in the buffer to determine and generate an optimized set of one or more additional commands to insert after one or more corresponding selected read-requests in the sequence of read-requests that minimizes the number of clock cycles required to process the current sequence of read-requests;
- and
- transmit each additional command of the optimized set to the memory controller during one or more idle cycles after the corresponding selected read-request, wherein idle cycles correspond to cycles used to read data in response to each read-request;
- and
- wherein the memory controller is operable to process the additional commands.
A method comprising:
- receiving and storing a sequence of two or more read-requests in a buffer;
- transmitting a pending read-request from the buffer to a memory controller;
- and
- conditionally generating and transmitting one or more additional commands to the memory controller during one or more idle cycles after transmitting the pending read request and before transmitting a next pending read-request to the memory controller, wherein the one or more idle cycles correspond to cycles used to read data in response to the pending read-request;
- wherein said conditionally generating comprises analyzing the sequence of read-requests stored in the buffer to determine and generate an optimized set of one or more additional commands to insert after one or more selected read-requests in the sequence of read-requests that minimizes the number of clock cycles required to process the sequence of read-requests.
Dependencies are inferred from the claim text.