Low-noise, high-linearity analog multiplier
AssigneeSTMicroelectronics S.r.l.
InventorsSimone Erba, Giampiero Montagna, Mario Valla
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AssigneeSTMicroelectronics S.r.l.
InventorsSimone Erba, Giampiero Montagna, Mario Valla
Estimating the term…
An analog multiplier for multiplying a first analog voltage signal at a first frequency by a second analog voltage signal at a second frequency, comprising a first stage for converting the first analog voltage signal into a first and a second current signals, and a second stage comprising a first and a second cross-coupled current-switching pairs, driven by the second voltage signal, the first and second current-switching pairs having respective current inputs for receiving the first and the second current signals, respectively. Parasitic capacitances are inherently associated with each current input of the current-switching pairs. A compensation circuit is coupled to the current inputs of the current-switching pairs for compensating the parasitic capacitances.
An analog multiplier for multiplying a first analog voltage signal at a first frequency by a second analog voltage signal at a second frequency, comprising:
A method of improving linearity and reducing noise in an analog multiplier including a first stage for converting a first analog voltage signal at a first frequency into a first and a second current signals, and a second stage comprising a first and a second cross-coupled current-switching pairs, driven by a second voltage signal at a second frequency, said first and second current-switching pairs having respective current inputs for receiving the first and the second current signals, respectively, the method comprising:
A mixer, comprising:
A mixer, comprising:
An electronic system, comprising:
A method, comprising:
A circuit, comprising:
A method, comprising:
Dependencies are inferred from the claim text.