Semiconductor devices having a hybrid channel layer, current aperture transistors and methods of fabricating same
AssigneeCree, Inc.
InventorAdam William Saxler
Life of this patent
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Abstract
Transistors and/or methods of fabricating transistors that include a source contact, drain contact and gate contact are provided. In some embodiments, a channel region is provided between the source and drain contacts and at least a portion of the channel regions includes a hybrid layer comprising semiconductor material. In particular embodiments of the present invention, the transistor is a current aperture transistor. The channel region may include pendeo-epitaxial layers or epitaxial laterally overgrown layers. Transistors and methods of fabricating current aperture transistors that include a trench that extends through the channel and barrier layers and includes semiconductor material therein are also provided.
Claims45
A transistor comprising a source contact, a drain contact and a gate contact and a channel region between the source and drain contacts at least a portion of which comprises a hybrid layer comprising semiconductor material, wherein the transistor comprises a current aperture transistor and wherein a portion of the channel region through the current aperture comprises a vertical portion and a horizontal portion.
A transistor comprising a source contact, a drain contact and a gate contact and a channel region between the source and drain contacts at least a portion of which comprises a hybrid layer comprising semiconductor material:
- a first n-type nitride-based layer on a substrate, the first n-type nitride-based layer having a first surface opposite the substrate and having an aperture having a sidewall;
- a nitride-based layer on the first n-type nitride-based layer and extending onto the sidewall of the aperture, where a portion of the nitride-based layer on the sidewall of the aperture is n-type and a portion of the nitride-based layer on the first surface of the first n-type nitride-based layer is p-type and/or insulating;
- an unintentionally doped nitride-based layer on the nitride based layer and extending to substantially fill the aperture, the unintentionally doped nitride-based layer having a portion of n-type nitride-based semiconductor material on the n-type portion of the nitride-based layer;
- first and second layers of nitride-based semiconductor material on the unintentionally doped nitride-based layer and configured to provide a two-dimensional electron gas (2DEG) in a region of an interface between the first and second semiconductor material layers;
- and
- wherein the source contact and the gate contact are provided on the second layer comprising nitride-based semiconductor material and the drain contact is electrically connected to the first n-type nitride-based layer.
A transistor comprising:
- a substrate having a trench therein;
- a first pendeo-epitaxial layer comprising semiconductor material of the substrate and having spaced apart cantilevered portions that extend over the trench;
- a second pendeo-epitaxial layer comprising semiconductor material of a second conductivity type and/or insulating on the first pendeo-epitaxial layer comprising semiconductor material and that includes spaced apart portions that extend from end surfaces of the cantilevered portions of the first pendeo-epitaxial layer that are the first conductivity type;
- a third pendeo-epitaxial layer comprising unintentionally doped semiconductor material on the second pendeo-epitaxial layer and that includes portions that extend from the spaced apart portions and coalesce and are the first conductivity type;
- a channel layer comprising semiconductor material on the third pendeo-epitaxial layer;
- a barrier layer on the channel layer;
- a source contact on the barrier layer;
- a gate contact on the barrier layer;
- and
- a drain contact electrically connected to the first layer comprising conformal semiconductor material.
A method of fabricating a transistor comprising:
- forming a channel region at least a portion of which comprises a hybrid layer comprising semiconductor material;
- and
- forming a source contact, a drain contact and a gate contact, wherein the channel region is between the source and drain contacts, wherein the transistor comprises a current aperture transistor and wherein a portion of the channel region through the current aperture comprises a vertical portion and a horizontal portion.
A method of fabricating a transistor comprising:
- forming a channel region at least a portion of which comprises a hybrid layer comprising semiconductor material;
- and
- forming a source contact, a drain contact and a gate contact, wherein the channel region is between the source and drain contacts, wherein forming a channel region at least a portion of which comprises a hybrid layer comprising semiconductor material further comprises:
- forming a first n-type nitride-based layer on a substrate, the first n-type nitride-based layer having a first surface opposite the substrate and an aperture having sidewalls;
- forming a nitride-based layer on the first n-type nitride-based layer and extending onto the sidewalls of the aperture, where a portion of the nitride-based layer on the sidewalls of the aperture is n-type and a portion of the nitride-based layer on the first surface of the first n-type nitride-based layer is p-type and/or insulating;
- forming an unintentionally doped nitride-based layer on the nitride based layer and extending to substantially fill the aperture, the unintentionally doped nitride-based layer having portions of n-type nitride-based semiconductor material on the n-type portions of the nitride-based layer;
- forming first and second layers of nitride-based semiconductor material on the unintentionally doped nitride-based layer and configured to provide a two-dimensional electron gas (2DEG) in a region of an interface between the first and second semiconductor material layers;
- and
- wherein the source contact and the gate contact are formed on the second layer comprising nitride-based semiconductor material and the drain contact is electrically connected to the first n-type nitride-based layer.
A method of fabricating a transistor comprising:
- forming a trench in a substrate;
- forming a first pendeo-epitaxial layer comprising semiconductor material of a first conductivity type by pendeo-epitaxial growth on the substrate and having spaced apart cantilevered portions that extend over the trench;
- forming a second pendeo-epitaxial layer comprising semiconductor material of a second conductivity type and/or insulating by pendeo-epitaxial growth on the first pendeo-epitaxial layer comprising semiconductor material and that includes spaced apart portions that extend from end surfaces of the cantilevered portions of the first pendeo-epitaxial layer that are the first conductivity type;
- forming a third pendeo-epitaxial layer comprising unintentionally doped semiconductor material by pendeo-epitaxial growth on the second pendeo-epitaxial layer and that includes portions that extend from the spaced apart portions and coalesce and are the first conductivity type;
- forming a channel layer comprising semiconductor material on the third pendeo-epitaxial layer;
- forming a barrier layer on the channel layer;
- forming a source contact on the barrier layer;
- forming a gate contact on the barrier layer;
- and
- forming a drain contact electrically connected to a first conformal layer comprising semiconductor material.
Dependencies are inferred from the claim text.