# US 7,079,490 B1 · Integrated circuit with trace analyzer > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 7,079,490 B1 - Document ID: US7079490B1 - Status: Granted - Kind: B1 - Application number: 09/204,257 - Filed: 1998-12-03 - Granted: 2006-07-18 - Earliest claimed: 1998-12-03 - Assignees: Intel Corporation - Inventors: Frank Hady; Rick Coulson - Web page: https://patentgrep.com/patent/US7079490B1 ## CPC - G01R 31/3177: Testing of logic operation, e.g. by logic analysers - G01R: MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES (indicating correct tuning of resonant circuits H03J3/12) ## Abstract An integrated circuit includes a trace analyzer to sample, process and store data carried along internal or external data path of the circuit. The trace analyzer may include a multiplexer, a sampler, a formatter and a memory controller. The trace analyzer samples data on a predetermined basis, processes it and caused the processed data to be stored in a memory. ## Claims ### Claim 1 A bridge interface, comprising: a plurality of mutually interconnected multiplexers comprising at least three multiplexers, a plurality of communication paths composed of interconnections between the plurality of mutually interconnected multiplexers, each multiplexer being separately interconnected with every other multiplexer of the plurality of mutually interconnected multiplexers, at least two of the communication paths being active simultaneously, and a trace analyzer having input ports with connected to each of the plurality of communication paths, the analyzer to capture data from a selected one of the communication paths. ### Claim 2 (depends on 1) The bridge interface of claim 1, wherein the trace analyzer includes an output port in communication with one of the multiplexers. ### Claim 3 (depends on 1) The bridge interface of claim 1, wherein the trace analyzer comprises: a multiplexer to receive the trace analyzer inputs, a sampler in communication with the multiplexer, and a memory controller in communication with the sampler. ### Claim 4 (depends on 3) The bridge interface of claim 3, wherein the memory controller includes an output in communication with one of the plurality of mutually interconnected multiplexers. ### Claim 5 (depends on 3) The bridge interface of claim 3, wherein the trace analyzer further comprises a controller provided in communication with the multiplexer of the trace analyzer. ### Claim 6 (depends on 1) The bridge interface of claim 1, wherein the plurality of interconnected multiplexers are fixedly interconnected by the plurality of communication paths, each of the input ports being fixedly connected to a respective one of the communications paths in between the plurality of mutually interconnected multiplexers. ### Claim 7 A bridge interface, comprising: a plurality of mutually interconnected multiplexers, a plurality of communication paths formed by each multiplexer being separately interconnected with every other multiplexer of the plurality of mutually interconnected multiplexers, at least two of the communication paths being active simultaneously, and a trace analyzer having input ports in communication with each of the plurality of communication paths, the analyzer to capture data from a selected one of the communication paths, wherein the trace analyzer comprises: a multiplexer to receive the trace analyzer inputs, a sampler in communication with the multiplexer, and a memory controller in communication with the sampler, and wherein the trace analyzer further comprises a formatter provided in communication with the sampler and having a output port in communication with the memory controller. ### Claim 8 A bridge interface, comprising: a plurality of mutually interconnected multiplexers comprising at least three multiplexers, each multiplexer to selectively pass data from one of a plurality of discrete data paths connected to the respective multiplexer, each of the plurality of discrete data paths of a connected to the respective multiplexer connecting to another multiplexer among the plurality of multiplexers, the discrete data paths interconnecting each of the multiplexers with every other multiplexer of the plurality of multiplexers, and a trace analyzer having input ports connected to each of the discrete data paths interconnecting the plurality of mutually interconnected multiplexers, wherein the trace analyzer and the plurality of multiplexers are provided within an integrated circuit chip. ### Claim 9 (depends on 8) The bridge interface of claim 8, wherein the trace analyzer includes an output port in communication with one of the bridge interface multiplexers. ### Claim 10 (depends on 8) The bridge interface of claim 8, wherein the trace analyzer further comprises: a trace analyzer multiplexer to receive trace analyzer inputs via the input ports, a sampler in communication with the trace analyzer multiplexer, and a memory controller in communication with the sampler. ### Claim 11 (depends on 10) The bridge interface of claim 10, wherein the trace analyzer further comprises a controller provided in communication with the multiplexer of the trace analyzer. ### Claim 12 (depends on 8) The bridge interface of claim 8, wherein each of the paths of the respective multiplexers fixedly extend to another multiplexer among the plurality of multiplexers, each of the input ports being fixedly connected to a respective one of the data paths in between the plurality of mutually interconnected multiplexers, the data paths fixedly interconnecting each of the multiplexers with every other multiplexer of the plurality of multiplexers. ### Claim 13 A bridge interface, comprising: a plurality of mutually interconnected multiplexers, each multiplexer having a plurality of discrete data paths, each data path extending to every other multiplexer among the plurality of multiplexers, and a trace analyzer having input ports in communication the data paths, wherein the trace analyzer and the plurality of multiplexers are provided within an integrated circuit chip, wherein the trace analyzer further comprises: a trace analyzer multiplexer to receive trace analyzer inputs via the input ports, a sampler in communication with the trace analyzer multiplexer, and a memory controller in communication with the sampler, and wherein the memory controller includes an output in communication with one of the plurality of mutually interconnected bridge interface multiplexers. ### Claim 14 A bridge interface, comprising: a plurality of mutually interconnected multiplexers, each multiplexer having a plurality of discrete data paths, each data path extending to every other multiplexer among the plurality of multiplexers, and a trace analyzer having input ports in communication the data paths, wherein the trace analyzer and the plurality of multiplexers are provided within an integrated circuit chip, wherein the trace analyzer further comprises: a trace analyzer multiplexer to receive trace analyzer inputs via the input ports, a sampler in communication with the trace analyzer multiplexer, and a memory controller in communication with the sampler, and wherein the trace analyzer further comprises a formatter provided in communication with the sampler and having an output port in communication with the memory controller. ### Claim 15 A bridge interface, comprising: a plurality of mutually interconnected multiplexers, each multiplexer having a separate bus extending to each of the other multiplexers, and a trace analyzer comprising: input ports in communication with each of the buses, a trace analyzer multiplexer connected to the input ports, a sampler to receive an input from the trace analyzer multiplexer, and a memory controller in communication with the sampler, the trace analyzer and the plurality of multiplexers being provided within a single integrated circuit chip, wherein the memory controller comprises an output coupled to one of the plurality of mutually interconnected multiplexers. ### Claim 16 (depends on 15) The bridge interface of claim 15, wherein the trace analyzer further comprises a controller coupled to the multiplexer of the trace analyzer. ### Claim 17 A bridge interface, comprising: a plurality of mutually interconnected multiplexers, each multiplexer having a separate bus extending to each of the other multiplexers, and a trace analyzer comprising: input ports in communication with each of the buses, a trace analyzer multiplexer connected to the input ports, a sampler to receive an input from the trace analyzer multiplexer, and a memory controller in communication with the sampler, the trace analyzer and the plurality of multiplexers being provided within a single integrated circuit chip, wherein the trace analyzer further comprises a formatter coupled to the sampler and an output coupled to the memory controller. ### Claim 18 (depends on 17) The bridge interface of claim 17, wherein the trace analyzer further comprises a controller coupled to the multiplexer of the trace analyzer. ### Claim 19 A bridge interface, comprising: a plurality of multiplexers comprising at least three multiplexers, a plurality of discrete communication paths, with a respective discrete communication path interconnecting each pair of multiplexers of the plurality of multiplexers, each multiplexer of the plurality of multiplexers being interconnected with every other multiplexer of the plurality of multiplexers, a trace analyzer comprising input ports coupled to each of the discrete communication paths between each pair of multiplexers, wherein the trace analyzer and the plurality of multiplexers are provided within a single integrated circuit chip. ### Claim 20 (depends on 19) The bridge interface of claim 19, wherein the discrete communication paths fixedly interconnect each pair of multiplexers of the plurality of multiplexers to each other. ### Claim 21 A system, comprising: a bridge interface chip coupled to a at least three external communication paths, the bridge interface chip comprising: a plurality of multiplexers comprising at least three multiplexers, with a respective multiplexer associated with each of the external communication paths, each multiplexer coupled to each of the other multiplexers by a respective discrete internal communication path, the internal communications paths interconnecting each of the multiplexers with every other multiplexer of the plurality of multiplexers; and a trace analyzer to capture signals on the internal communication paths, the trace analyzer coupled to each of the internal communication paths between the plurality of multiplexers by an internal multiplexer, the trace analyzer having an output coupled to one of the plurality of multiplexers, and a system memory chip coupled to the bridge interface chip by one of the external communication paths, the external communication path coupled to one the plurality multiplexer that is also coupled to the output of the trace analyzer. ### Claim 22 (depends on 21) The system of claim 21, wherein the trace analyzer comprises: the internal multiplexer to receive the trace analyzer inputs, a sampler in communication with the internal multiplexer, and a memory controller in communication with the sampler. ### Claim 23 (depends on 22) The system of claim 22, wherein the trace analyzer further comprises a controller provided in communication with the internal multiplexer of the trace analyzer. ### Claim 24 (depends on 21) The system of claim 21, wherein each multiplexer is fixedly coupled to each of the other multiplexers by the respective discrete internal communication path, the internal communications paths fixedly interconnecting each of the multiplexers with every other multiplexer of the plurality of multiplexers. ### Claim 25 A system, comprising: a bridge interface chip coupled to a plurality of external communication paths, the bridge interface chip comprising: a plurality of multiplexers associated with each of the external communication paths, each multiplexer coupled to every other multiplexer by a discrete internal communication path; and a trace analyzer to capture signals on each discrete internal communication path coupling the plurality of multiplexers, the trace analyzer coupled to the internal communication paths by an internal multiplexer, the trace analyzer having an output coupled to one of the plurality of multiplexers, and a system memory chip coupled to the bridge interface chip by one of the external communication paths, the external communication path coupled to one the plurality multiplexer that is also coupled to the output of the trace analyzer, wherein the trace analyzer comprises: the internal multiplexer to receive the signals on each of the discrete internal communication paths as inputs, a sampler in communication with the internal multiplexer, and a memory controller in communication with the sampler, and wherein the memory controller includes an output in communication with one of the plurality of multiplexers that is also coupled to the external communication path of the system memory chip.