# US 7,079,444 B2 · Memory system using simultaneous bi-directional input/output circuit on an address bus line > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 7,079,444 B2 - Document ID: US7079444B2 - Status: Granted - Kind: B2 - Application number: 10/974,951 - Filed: 2004-10-28 - Published: 2005-09-01 - Granted: 2006-07-18 - Earliest claimed: 2004-02-26 - Assignees: Samsung Electronics Co., Ltd. - Inventors: Jung-bae Lee - Web page: https://patentgrep.com/patent/US7079444B2 ## CPC - G11C 7/10: Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers - G06F 11/1044: {with specific ECC/EDC distribution} - G06F 13/1668: {Details of memory controller} - G11C 7/1051: {Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits} - G11C 7/1078: {Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits} - G11C 8/06: Address interface arrangements, e.g. address buffers - G11C: STATIC STORES (semiconductor memory devices H10B) - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract A memory system using a simultaneous bi-directional input/output (SBD I/O) circuit on an address bus line. The memory system includes a first address I/O circuit and a second address I/O circuit, which are connected by the address bus line. The first address I/O circuit may be included in a controller, transmits an address signal to the address bus line, and receives an acknowledgement signal from the address bus line. The second address I/O circuit may be included in a memory device (such as dynamic random access memory (DRAM)), transmits the acknowledgement signal to the address bus line, and receives the address signal from the address bus line. The memory system may also include an error correction circuit unit which generates the acknowledgement signal indicating if an error is present in the address signal received by the second address I/O circuit. ## Claims ### Claim 1 A memory system, comprising: an address bus line; a first address input/output circuit connected to the address bus line, wherein the first address input/output circuit transmits an address signal to the address bus line and receives an acknowledgement signal which indicates if an error is present in the address signal from the address bus line; and a second address input/output circuit connected to the address bus line, wherein the second address input/output circuit transmits the acknowledgement signal to the address bus line and receives the address signal from the address bus line. ### Claim 2 (depends on 1) The memory system of claim 1, wherein the first address input/output circuit is comprised in a controller of the memory system. ### Claim 3 (depends on 1) The memory system of claim 1, wherein the first address input/output circuit comprises: an output driver which outputs the address signal to the address bus line; and an input buffer which receives the acknowledgement signal from the address bus line as an input acknowledgement signal, according to a voltage level of the address bus line and a reference voltage level. ### Claim 4 (depends on 3) The memory system of claim 3, wherein the input buffer comprises a differential amplifier which compares the voltage level of the address bus line and the reference voltage level. ### Claim 5 (depends on 1) The memory system of claim 1, wherein the second address input/output circuit is comprised in a memory device within the memory system. ### Claim 6 (depends on 1) The memory system of claim 1, wherein the second address input/output circuit comprises: an output driver which outputs the acknowledgement signal to the address bus line; and an input buffer which receives the address signal from the address bus line as an input address signal, in response to a voltage level of the address bus line and a reference voltage level. ### Claim 7 (depends on 6) The memory system of claim 6, wherein the input buffer comprises a differential amplifier which compares the voltage level of the address bus line and the reference voltage level. ### Claim 8 (depends on 1) The memory system of claim 1, wherein the first input/output circuit is comprised in a controller of the memory system, wherein the second input/output circuit is comprised in a memory device of the memory system, and wherein said memory system further comprises simultaneous bi-directional data line coupled between the controller and the memory device. ### Claim 9 A memory system, comprising: an address bus line; a first address input/output circuit connected to the address bus line, wherein the first address input/output circuit transmits an address signal to the address bus line and receives an acknowledgement signal from the address bus line; a second address input/output circuit connected to the address bus line, wherein the second address input/output circuit transmits the acknowledgement signal to the address bus line and receives the address signal from the address bus line; and an error correction circuit unit which generates the acknowledgement signal, wherein the acknowledgment signal indicates if an error is present in the address signal received by the second address input/output circuit. ### Claim 10 (depends on 9) The memory system of claim 9, wherein the error correction circuit unit corrects an error in the address signal. ### Claim 11 (depends on 9) The memory system of claim 9, wherein the error correction circuit unit comprises: a parity bit generation circuit which generates “p” parity bits by combining “m” bit-address signals received from the address bus line; a check bit generation circuit which generates “c” check bits by combining the “m” bit-address signals and the “p” parity bits; and an error correction circuit which corrects an error in the “m” bit-address signals in response to syndrome data comprising the “c” check bits. ### Claim 12 (depends on 11) The memory system of claim 11, wherein the parity bit generation circuit generates the “p” parity bits by selectively subjecting the “m” bit-address signals to an exclusive-OR operation. ### Claim 13 (depends on 11) The memory system of claim 11, wherein the check bit generation circuit generates the syndrome data comprising the “c” check bits by selectively exclusive-ORing the “m” bit-address signals and the “p” parity bits and latching a result of the exclusive-ORing in response to a clock signal. ### Claim 14 (depends on 13) The memory system of claim 13, wherein the syndrome data indicates a position of an address signal having an error among the “m” bit-address signals. ### Claim 15 (depends on 11) The memory system of claim 11, wherein the error correction circuit comprises: a NAND gate which receives the syndrome data; a first inverter which receives an output of the NAND gate; a second inverter which receives a bit-address signal among the “m” bit-address signals; a first N-type metal oxide semiconductor (NMOS) transistor which transmits the bit-address signal as an error-corrected bit-address signal in response to the output of the NAND gate; and a second NMOS transistor which transmits an output of the second inverter as the error-corrected bit-address signal, in response to an output of the first inverter. ### Claim 16 (depends on 9) The memory system of claim 9, wherein the first address input/output circuit is comprised in a controller within the memory system. ### Claim 17 (depends on 9) The memory system of claim 9, wherein the first address input/output circuit comprises: an output driver which outputs the address signal to the address bus line; and an input buffer which receives the acknowledgement signal from the address bus line as an input acknowledgement signal, according to a voltage level of the address bus line and a reference voltage level. ### Claim 18 (depends on 17) The memory system of claim 17, wherein the input buffer comprises a differential amplifier which compares the voltage level of the address bus line and the reference voltage level. ### Claim 19 (depends on 9) The memory system of claim 9, wherein the second address input/output circuit is comprised in a memory device. ### Claim 20 (depends on 9) The memory system of claim 9, wherein the second address input/output circuit comprises: an output driver which outputs the acknowledgement signal to the address bus line; and an input buffer which receives the address signal from the address bus line as an input address signal, in response to a voltage level of the address bus line and a reference voltage level. ### Claim 21 (depends on 20) The memory system of claim 20, wherein the input buffer comprises a differential amplifier which compares the voltage level of the address bus line and the reference voltage level. ### Claim 22 (depends on 9) The memory system of claim 9, wherein the first input/output circuit is comprised in a controller of the memory system, wherein the second input/output circuit is comprised in a memory device of the memory system, and wherein said memory system further comprises simultaneous bi-directional data line coupled between the controller and the memory device.