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US 7,079,059 B2Granted
ADC with digital error correction
AssigneeAcqiris
InventorNeil Adams
Life of this patent
Estimating the term…
Abstract
Interleaved Analogue to Digital converter, comprising a plurality of individual ADCs (71). A digital filter stage (20) is used for equalizing the responses of the individual ADCs, and comprises a FIR filter in which the coefficient table is cyclically reloaded between ADCs' samples, in order to reduce the number of multipliers required.
Claims13
An analogue to Digital converter circuit comprising,
- a plurality of individual ADCs, each of said individual ADCs having an individual response,
- a clock generating circuit for clocking said individual ADCs, wherein said individual ADCs and said clock generating circuit are arranged to generate samples of the amplitude of an input signal by said individual ADCs one at a time in an cyclical ADC sequence,
- a digital filter for correcting differences between said individual responses,
- said digital filter comprising computing means, for computing a function of said samples by said individual ADCs, said function depending on a coefficient table loaded into said filter, wherein said digital filter comprises coefficient loading means for changing said coefficient table synchronously with a transition of a signal of said clock generating circuit.
1 more element
A digital processing circuit for correcting digital signals produced by a plurality of interleaved individual digital sources, comprising:
- computing means for computing a function of digital samples by said individual digital sources, said function depending on a coefficient table loaded into said filter, wherein
- said digital filter comprises coefficient loading means for changing said coefficient table synchronously with the interleaving scheme of said individual digital sources.
An analogue to Digital converter circuit comprising,
- a plurality of N individual ADCs, with N being an integer greater than one and each of said individual ADCs having an individual response,
- a clock generating circuit for clocking said individual ADCs, wherein said individual ADCs and said clock generating circuit are arranged to generate samples of the amplitude of an input signal by said individual ADCs one at a time in an cyclical ADC sequence,
- a digital filter for correcting differences between said individual responses,
- said digital filter comprising computing means, for computing a function of said samples by said individual ADCs, said function depending on a coefficient table loaded into said filter, wherein
- said digital filter comprises coefficient loading means for loading said coefficient table synchronously with a transition of a signal of said clock generating circuit, and further wherein
- the ADCs are clocked at a frequency F/N, whereas the filter and/or said loading is clocked at a frequency F.
3 more elements
Dependencies are inferred from the claim text.