Thyristor-based memory and its method of operation
AssigneeT-RAM Semiconductor, Inc.
InventorsFarid Nemati, Kevin J. Yang
Life of this patent
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Abstract
A thyristor-based memory may comprise a thyristor accessible via an access transistor. A temperature dependent bias may be applied to at least one of a supporting substrate and an electrode capacitively-coupled to a base region of the thyristor. The voltage level of the adaptive bias may change with respect to temperature and may influence and/or compensate an inherent bipolar gain of the thyristor in accordance with the change in bias and may enhance its performance and/or reliability over a range of operating temperature. In a particular embodiment, the thyristor may be formed in a layer of silicon of an SOI substrate and the adaptive bias coupled to a supporting substrate of the SOI structure.
Claims10
A semiconductor device comprising:
- a plurality of memory cells, at least one of the memory cells comprising:
- a thyristor, and
- an electrode disposed over a region of the thyristor and operable under bias to effect an electric field therein;
- and
- a bias circuit to bias the electrode with a voltage level dependent on temperature;
- said device further comprising:
- supporting material comprising at least one of semiconductor and conductor material;
- an insulating material over the supporting material;
- the thyristor formed in a layer of silicon disposed over the insulating material;
- and
- dielectric disposed between the electrode and the layer of silicon;
- the bias circuit operable to define the voltage for the electrode relative to that of the supporting material.
A semiconductor device comprising:
- a layer of silicon disposed in insulated relationship over a supporting substrate;
- a plurality of memory cells, at least one of the memory cells comprising:
- a thyristor comprising N-P-N-P doped regions in the layer of silicon for respective cathode-emitter, P-base, N-base and anode-emitter regions of the thyristor, and
- an electrode capacitively coupled to one of the N-base and P-base regions;
- and
- a bias circuit to sense a temperature and vary the voltage level for a bias to at least one of the electrode and the supporting substrate dependent on the temperature.
A semiconductor device comprising:
- a plurality of memory cells, at least one of the memory cells comprising:
- a thyristor, and
- an electrode disposed over a region of the thyristor;
- and
- a bias circuit to bias the electrode with a voltage dependent on a temperature, the bias circuit to influence a gain of a bipolar device of the thyristor dependent on the temperature.
A thyristor memory device, comprising:
- a thyristor formed in semiconductor material, the thyristor comprising:
- an anode/cathode,
- a cathode/anode, and
- first and second base regions disposed in contiguous series relationship between the anode/cathode and the cathode/anode;
- an electrode over one of the first and second base regions and operable under bias to affect an electric field therein;
- and
- a temperature dependent bias circuit to bias the electrode with a voltage dependent on the temperature.
A semiconductor memory device comprising:
- a supporting substrate;
- an insulating layer over the supporting substrate;
- a thyristor comprising N-P-N-P doped regions in contiguous serial relationship in a layer of silicon over the insulating layer, the N-P-N and the P-N-P sequences of the thyristor representative of respective bipolar transistors;
- and
- means for setting a bias voltage of the electrode dependent on temperature to establish an electric field through the base region between the electrode and the supporting substrate, and to influence a gain of its respective one of the N-P-N and P-N-P bipolar transistors dependent on the temperature.
Dependencies are inferred from the claim text.