# US 7,076,598 B2 · Pipeline accessing method to a large block memory

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- Number: US 7,076,598 B2
- Document ID: US7076598B2
- Status: Granted
- Kind: B2
- Application number: 10/605,099
- Filed: 2003-09-09
- Published: 2005-03-10
- Granted: 2006-07-11
- Earliest claimed: 2003-09-09
- Assignees: Solid State System Co., Ltd.
- Inventors: Chih-Hung Wang
- Web page: https://patentgrep.com/patent/US7076598B2

## CPC

- G06F 12/0246: {in block erasable memory, e.g. flash memory}
- G06F 2212/7203: Temporary buffering, e.g. using volatile buffer or dedicated buffer blocks
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

A pipeline accessing method to a large block memory is described. The large block flash memory has a plurality of pages and each page has a plurality of sectors. The memory device has a controller to control an access operation between a host and a cell array of the large block flash memory with a page buffer. The controller includes at least two buffers, when the host intends to program the memory device. In the method, data sectors are transferred between the host and the large block flash memory by alternatively using the buffers. After transferring N data sectors with respect to one page, a start program command is issued by the controller for programming the data.

## Claims

### Claim 1

A method of accessing a large block memory of a nonvolatile memory device, wherein the large block memory has a plurality of pages and each page has a plurality of sectors, wherein the memory device has a controller to control an access operation between a host and the large block memory of the memory device, the controller also has two buffers regions, the method comprising:
transferring a portion of a current page data from the host to the controller, and transferring a portion of the current page data from die controller to a data cache within the large block memory, wherein the two transferring steps can be performed at the same time;
shifting the current page data in the data cache to a page buffer within the large block memory, when full data of one page is received and a storage space of the page buffer is available; and
programming the current page data into a cell array of the large block memory, and simultaneously performing the foregoing two transferring steps if a next page data is desired to continuously transfer.

### Claim 2 (depends on 1)

The method of claim 1, wherein in the step of shifting the current page data in the data cache to the page buffer, a command is issued to perform the step.

### Claim 3 (depends on 1)

The method of claim 1, wherein in a time period, at least two of the two transferring steps and the programming step are performed at the same time.

### Claim 4 (depends on 1)

The method of claim 1, wherein in a time period, all of the two transferring steps and the programming step are performed at the same time.

### Claim 5 (depends on 1)

The method of claim 1, wherein when a last page is received, a start program command is issued to program the memory cell array.

### Claim 6

A method of accessing a large block memory of a nonvolatile memory device, wherein the large block memory has a plurality of pages and each page has a plurality of sectors, wherein the memory device has a controller to control an access operation between a host and the large block memory of the memory device, the controller also has two buffers regions, the method comprising:
transferring a portion of a current page data from the host to the controller, and transferring a portion of the current page data from the controller to a data cache within the large block memory, wherein the two transferring stens can be performed at the same time;
shifting the current page data in the data cache to a page buffer within the large block memory;
programming the current page data into a cell array of the large block memory, and simultaneously performing the foregoing two transferring steps if a next page data is desired to continuously transfer; wherein
before a last page is received, a “start program with data cache” command is issued for simultaneously receiving the data at the data cache and programming the data at page buffer into the cell array of the large block memory.