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US 7,075,161 B2Granted
Apparatus and method for making a low capacitance artificial nanopore
AssigneeAgilent Technologies, Inc.
InventorPhillip W. Barth
Life of this patent
Estimating the term…
Abstract
An apparatus and method for making a nanopore chip exhibiting low capacitance. The apparatus provides a thin diaphragm on a rigid semiconductor frame suitable for nanopore fabrication, the diaphragm having associated thicker insulator regions to reduce capacitance. Also disclosed is a method of making the apparatus.
Claims34
An apparatus for the construction of one of a microscale and nanoscale device, comprising:
- a first region comprising a diaphragm, the diaphragm comprising a first insulator material, the diaphragm having a top surface and a bottom surface,
- a second region comprising a second insulator material laterally surrounding the first region and having an upper surface substantially flush with the bottom surface of the first region,
- a substrate region comprising semiconductor material supporting the first region, the semiconductor material comprising a rigid frame laterally surrounding the diaphragm, wherein the second region is positioned between a portion of the bottom surface of the first region and a portion of an upper surface of the substrate region,
- a substrate cavity region beneath the diaphragm,
- a third region comprising a third insulator material, the third region being disposed atop the diaphragm, the third region being substantially thicker than the diaphragm and having a third cavity therethrough exposing a portion of the top surface of the diaphragm, the exposed portion of the top surface of the diaphragm being suitable for fabrication of one of a microscale and a nanoscale device.
2 more elements
An apparatus for the construction of one of a microscale and nanoscale device, comprising:
- a first region comprising a diaphragm, the diaphragm comprising a first insulator material, the diaphragm having a top surface and a bottom surface,
- a second region comprising a second insulator material laterally surrounding the first region and having an upper surface substantially flush with the bottom surface of the first region,
- a substrate region comprising semiconductor material supporting the first region, the semiconductor material comprising a rigid frame laterally surrounding the diaphragm, wherein the second region is positioned between a portion of the bottom surface of the first region and a portion of an upper surface of the substrate region,
- a substrate cavity region beneath the diaphragm,
- a third region comprising a third insulator material, the third region being disposed atop the diaphragm, the third region being substantially thicker than the diaphragm and having a third cavity therethrough exposing a portion of the top surface of the diaphragm, the exposed portion of the top surface of the diaphragm being suitable for fabrication of one of a microscale and a nanoscale device,
- wherein the third insulator material provides for low-capacitance across the top surface of the diaphragm.
3 more elements
An apparatus for the construction of one of a microscale and nanoscale device, comprising:
- a first region comprising a diaphragm, the diaphragm comprising a first insulator material, the diaphragm having a top surface and a bottom surface,
- a second region comprising a second insulator material laterally surrounding the first region and having an upper surface substantially flush with the bottom surface of the first region,
- a substrate region comprising semiconductor material supporting the first region, the semiconductor material comprising a rigid frame laterally surrounding the diaphragm, wherein the second region is positioned between a portion of the bottom surface of the first region and a portion of an upper surface of the substrate region,
- a substrate cavity region beneath the diaphragm,
- a third region comprising a third insulator material, the third region being disposed atop the diaphragm, the third region being substantially thicker than the diaphragm and having a third cavity therethrough exposing a portion of the top surface of the diaphragm, the exposed portion of the top surface of the diaphragm being suitable for fabrication of one of a microscale and a nanoscale device, and
- a microfluidic lead, said lead being disposed at a location comprising one of beneath the third region, and atop the third region.
3 more elements
An apparatus for the construction of one of a microscale and nanoscale device, comprising:
- a first region comprising a diaphragm, the diaphragm comprising a first insulator material, the diaphragm having a top surface and a bottom surface,
- a second region comprising a second insulator material laterally surrounding the first region and having an upper surface substantially flush with the bottom surface of the first region,
- a substrate region comprising semiconductor material supporting the first region, the semiconductor material comprising a rigid frame laterally surrounding the diaphragm, wherein the second region is positioned between a portion of the bottom surface of the first region and a portion of an upper surface of the substrate region,
- a substrate cavity region beneath the diaphragm,
- a third region comprising a third insulator material, the third region being disposed atop the diaphragm, the third region being substantially thicker than the diaphragm and having a third cavity therethrough exposing a portion of the top surface of the diaphragm, the exposed portion of the top surface of the diaphragm being suitable for fabrication of one of a microscale and a nanoscale device, and
- a fifth material, the fifth material comprising a bottom layer portion of the diaphragm.
3 more elements
An apparatus for the construction of one of a microscale and nanoscale device, comprising:
- a first region comprising a diaphragm, the diaphragm comprising a first insulator material, the diaphragm having a top surface and a bottom surface,
- a second region comprising a second insulator material laterally surrounding the first region and having an upper surface substantially flush with the bottom surface of the first region,
- a substrate region comprising semiconductor material supporting the first region, the semiconductor material comprising a rigid frame laterally surrounding the diaphragm, wherein the second region is positioned between a portion of the bottom surface of the first region and a portion of an upper surface of the substrate region,
- a substrate cavity region beneath the diaphragm,
- a third region comprising a third insulator material, the third region being disposed atop the diaphragm, the third region being substantially thicker than the diaphragm and having a third cavity therethrough exposing a portion of the top surface of the diaphragm, the exposed portion of the top surface of the diaphragm being suitable for fabrication of one of a microscale and a nanoscale device, and
- a sixth region comprising a sixth insulator material disposed atop the substrate region.
3 more elements
Dependencies are inferred from the claim text.