Constraints-directed compilation for heterogeneous reconfigurable architectures

A method comprising:

• mapping a plurality of functions into groups;
• placing the groups on resources within a heterogeneous reconfigurable device;
• the resources including a plurality of prourammable elements with different underlying architectures, wherein a first type of the plurality of programmable elements is capable of executing instructions, and a second type of the plurality of programmable elements is capable of different configurations to implement logic;
• estimating power consumption of the groups using a pre-determined database that estimates the power for each instruction or configuration, depending on the underlying architecture of a target programmable element type for each group;
• analyzing the groups for compliance with user-specified constraints, wherein the user-specified constraints include power consumption constraints;
• producing a mapped and placed design representation;
• profiling the design representation;
• and
• comparing results from the profiling with the user-specified constraints.

An apparatus including a medium to hold machine-accessible instructions that when accessed result in a machine performing:

• reading a design description for a heterogeneous reconfigurable device that includes a plurality of programmable elements with different underlying architectures, wherein a first type of the plurality of programmable elements is capable of executing instructions, and a second type of the plurality of programmable elements is capable of different confi2urations to implement logic, the design description including a plurality of functions to map to the plurality of programmable elements;
• combining the plurality of functions within the design description into groups based at least in part on possible programmable element types upon which the plurality of functions could successfully map;
• estimating power consumption of the groups using a pre-determined database that estimates the power for each instruction or configuration. depending on the underlying architecture of a target programmable element type for each group;
• and
• analyzing the groups for compliance with user-specified constraints, wherein the user-specified constraints include power consumption constraints.

An electronic system comprising:

• a processor;
• and
• a static random access memory to hold instructions that when accessed result in the processor performing reading a design description for a heterogeneous reconfigurable device that includes a plurality of programmable elements with different underlying architectures, wherein a first type of the plurality of programmable elements is capable of executing instructions, and a second type of the plurality of programmable elements is capable of different configurations to implement logic, the design description including a plurality of functions to map to the plurality of programmable elements;
• combining the plurality of functions within the design description into groups based at least in part on possible programmable element types upon which the plurality of functions could successfully map;
• estimating power consumption of the groups using a pre-determined database that estimates the power for each instruction or configuration, depending on the underlying architecture of a target programmable element type for each group;
• and analyzing the groups for compliance with user-specified constraints wherein the user-specified constraints include power consumption constraints.