Stability metrics for placement to quantify the stability of placement algorithms

A computer system comprising:

• means for processing program instructions;
• a memory device connected to said processing means;
• and
• program instructions residing in said memory device for quantifying the stability of a placement tool used in mapping the physical layout of logic cells for an integrated circuit chip, wherein said program instructions design a first layout of logic cells using the placement tool based on a first set of input parameters, design a second layout of the logic cells using the placement tool based on a second set of input parameters which is different from the first set of input parameters, calculate a stability value based on the movement of respective cell locations from the first layout to the second layout, and normalize the stability value based on respective cell locations in a third layout which is a random placement of the logic cells.

A method of quantifying the stability of a placement tool used in mapping the physical layout of logic cells for an integrated circuit chip, comprising the steps of:

• designing a first layout of logic cells using the placement tool based on a first set of input parameters;
• designing a second layout of the logic cells using the placement tool based on a second set of input parameters which is different from the first set of input parameters;
• and
• calculating a stability value based on the movement of respective cell locations from the first layout to the second layout, wherein said calculating step measures relative movement of logic cells with respect to the one or more nets of the layouts, and shifting of logic cells and symmetric reversal of logic cells about a net center does not contribute to the relative movement but spreading of logic cells and rotation of logic cells with respect to the net center does contribute to the relative movement.

A computer system comprising:

• means for processing program instructions;
• a memory device connected to said processing means;
• and
• program instructions residing in said memory device for quantifying the stability of a placement tool used in mapping the physical layout of logic cells for an integrated circuit chip, wherein said program instructions design a first layout of logic cells using the placement tool based on a first set of input parameters, design a second layout of the logic cells using the placement tool based on a second set of input parameters which is different from the first set of input parameters, and calculate a stability value based on the movement of respective cell locations from the first layout to the second layout, wherein relative movement of logic cells is measured with respect to the one or more nets of the layouts, and shifting of logic cells and symmetric reversal of logic cells about a net center does not contribute to the relative movement but spreading of logic cells and rotation of logic cells with respect to the net center does contribute to the relative movement.