Device, system and method for VLSI design analysis
AssigneeIntel Corporation
InventorsAlexander Novakovsky, Shy Shyman, Ziyad Hanna
Life of this patent
Estimating the term…
Abstract
A device, system and method for analysis of Very Large Scale Integration circuit designs. A computing platform may, for example, find one or more loops in a circuit design, functionally analyze the loops, and extract one or more Register-Transfer-level logical elements in relation to the analysis result. A computing platform may, for example, identify a group of at least one Channel Connected Sub-Network that forms at least one combinational loop, generate overall zero-delay collapsed functionality on an output of said group, identify one or more functional parts that form said group, and replace the group with one or more corresponding logically equivalent Register-Transfer-level devices.
Claims42
A method for VLSI design analysis, the method comprising:
- in a processor, finding a loop in a circuit design;
- in the processor, functionally analyzing the loop;
- in the processor, extracting a logical element in relation to an analysis result;
- and
- in the processor, automatically resolving the loop by performing an operation selected from a group consisting of:
- replacing the loop with a state element in a Finite State Machine level, and replacing the loop by a logically equivalent pure combinational non-loop logic.
An apparatus for VLSI design analysis, the apparatus comprising:
- a processor to find a loop in a circuit design, functionally analyze the loop, extract a logical element in relation to an analysis result, and automatically resolve the loop by performing an operation selected from a group consisting of:
- replacing the loop with a state element in a Finite State Machine level, and replacing the loop by a logically equivalent pure combinational non-loop logic.
An apparatus for VLSI design analysis, the apparatus comprising:
- a dynamic random access memory;
- and
- a processor to find a loop in a circuit design, functionally analyze the loop, extract a logical element in relation to an analysis result, and automatically resolve the loop by performing an operation selected from a group consisting of:
- replacing the loop with a state element in a Finite State Machine level, and replacing the loop by a logically equivalent pure combinational non-loop logic.
A machine-readable medium having stored thereon a set of instructions that, if executed by a machine, cause the machine to perform a method comprising:
- finding a loop in a circuit design;
- functionally analyzing the loop;
- extracting a logical element in relation to an analysis result;
- and
- automatically resolving the loop by performing an operation selected from a group consisting of:
- replacing the loop with a state element in a Finite State Machine level, and replacing the loop by a logically equivalent pure combinational non-loop logic.
Dependencies are inferred from the claim text.