Method and apparatus for generating bit errors in a forward error correction (FEC) system to estimate power dissipation characteristics of the system

A method for measuring power consumption in a forward error correction (FEC) system, the method comprising the steps of:

• generating bit sequences;
• FEC encoding the bit sequences to produce encoded N-bit sequences;
• generating a number of bit errors and inserting the number of bit errors into the encoded N-bit sequences to produce encoded N-bit error sequences containing a number K of bit errors;
• using an FEC decoder to FEC decode the encoded bit error sequences and correcting errors in the decoded sequences;
• and
• analyzing the decoded sequences to determine whether bit errors exist in the decoded sequences that were not corrected,
• and measuring the power consumption of the FEC system used in correcting errors in the decoded sequences.

An apparatus for generating and inserting bit errors in data words that have been encoded in a forward error correction (FEC) system, the apparatus comprising:

• a bit sequence generator configured to generate bit sequences;
• an FEC encoder, the FEC encoder being configured to encode bit sequences generated by the bit sequence generator;
• an FEC error vector generator, the FEC error vector generator being configured to generate error vectors and to utilize the error vectors to insert a number of errors into the encoded bit sequences to produce encoded bit error sequences;
• an FEC decoder, the FEC decoder being configured to decode the encoded bit error sequences and to correct any errors in the decoded sequences;
• and
• a detector, the detector being configured to analyze the decoded sequences and determine whether bit errors exist in the decoded sequences,
• wherein the number of errors inserted by the FEC error vector generator is a number that increases an amount of switching to be performed by logic gates in the FEC decoder beyond a nominal amount, and
• wherein if the detector determines that a single bit error was not corrected by the FEC decoder, the detector provides an indication that indicates to a user that a power distribution network that distributes power to the FEC decoder is not properly designed.

A method for measuring power consumption in a forward error correction (FEC) system, the method comprising the steps of:

• generating bit sequences;
• FEC encoding the bit sequences to produce encoded N-bit sequences;
• generating a number of bit errors and inserting the number of bit errors into the encoded N-bit sequences to produce encoded N-bit error sequences containing a number K of bit errors;
• using an FEC decoder to FEC decode the encoded bit error sequences and correcting errors in the decoded sequences;
• and
• analyzing the decoded sequences to determine whether bit errors exist in the decoded sequences that were not corrected,
• and measuring the power consumption of the FEC system used in correcting errors in the decoded sequences, and
• wherein if a determination is made during the analysis step that a single bit error was not corrected by the FEC decoder, an indication is provided that indicates to a user that a power distribution network that distributes power to the FEC decoder is not properly designed.

An apparatus for generating and inserting bit errors in data words that have been encoded in a forward error correction (FEC) system, the apparatus comprising:

• a bit sequence generator configured to generate bit sequences;
• an FEC encoder, the FEC encoder being configured to encode bit sequences generated by the bit sequence generator;
• an FEC error vector generator, the FEC error vector generator being configured to generate error vectors and to utilize the error vectors to insert a number of errors into the encoded bit sequences to produce encoded bit error sequences;
• an FEC decoder, the FEC decoder being configured to decode the encoded bit error sequences and to correct any errors in the decoded sequences;
• and
• a detector, the detector being configured to analyze the decoded sequences and determine whether bit errors exist in the decoded sequences,
• wherein the number of errors inserted by the FEC error vector generator is a number that increases an amount of switching to be performed by logic gates in the FEC decoder beyond a nominal amount, and
• wherein the number of errors inserted by the FEC error vector generator is a number that facilitates detection of a faulty design in a power distribution network that distributes power to the FEC decoder.

A method for measuring power consumption in a forward error correction (FEC) system, the method comprising the steps of:

• generating bit sequences;
• FEC encoding the bit sequences to produce encoded N-bit sequences;
• generating a number of bit errors and inserting the number of bit errors into the encoded N-bit sequences to produce encoded N-bit error sequences containing a number K of bit errors;
• using an FEC decoder to FEC decode the encoded bit error sequences and correcting errors in the decoded sequences;
• and
• analyzing the decoded sequences to determine whether bit errors exist in the decoded sequences that were not corrected,
• and measuring the power consumption of the FEC system used in correcting errors in the decoded sequences, and
• wherein the number of inserted bit errors is a number that facilitates detection of a faulty design in a power distribution network that distributes power to the FEC decoder.

A computer program for generating and inserting bit errors in data words that have been encoded in a forward error correction (FEC) system, the computer program being embodied on a computer-readable medium, the program comprising:

• a first code segment for generating bit sequences;
• a second code segment for FEC encoding the bit sequences to produce encoded N-bit sequences;
• a third code segment for generating bit errors and inserting the bit errors into the encoded N-bit sequences to produce encoded N-bit error sequences containing a number K of bit errors;
• a fourth code segment for FEC decoding the encoded bit error sequences and correcting errors in the decoded sequences;
• and
• a fifth code segment for analyzing the decoded sequences to determine whether bit errors exist in the decoded sequences that were not corrected,
• wherein the number K of bit errors is designed to maximize power consumption related to the FEC decoding, and
• wherein a determination is made during the analysis that one or more bit errors were not corrected by the fourth code segment causes the fifth code segment to detect a faulty design in a power distribution network.

A method for testing power consumption sufficiency in a forward error correction (FEC) system, the method comprising the steps of:

• generating bit sequences;
• FEC encoding the bit sequences to produce encoded N-bit sequences;
• determining the maximum number of bit errors K that can be corrected by the FEC system for the N-bit sequences;
• generating at least K bit errors and inserting K bit errors into the encoded N-bit sequences to produce encoded N-bit error sequences containing K of bit errors;
• using an FEC decoder to FEC decode the encoded bit error sequences and correcting errors in the decoded sequences;
• and
• analyzing the decoded sequences to determine whether bit errors exist in the decoded sequences that were uncorrected,
• wherein the number of inserted bit errors is a number that increases an amount of switching to be performed by logic gates in the FEC decoder beyond a nominal amount;
• and
• determining whether the power consumption of the FEC system used in correcting the K bit errors in the decoded sequences was sufficient based whether any uncorrected errors were not found in the decoded sequence analysis.