Test method for guaranteeing full stuck-at-fault coverage of a memory array

A computer program product embodied in a machine readable medium for testing stuck-at-faults in circuitry configured to determine matching of memory cell contents comprising the programming steps of:

• loading a first register with a first value, wherein said first register is configured to store contents for a row of a memory array;
• writing said first value into an entry in said memory array;
• loading a second register with a second value;
• loading a third register with one of said second value and a third value, wherein said second and said third values are pre-selected to test selector circuits for stuck-at-faults with a pattern, wherein said selector circuits are configured to determine matching of memory cell contents in said memory array, wherein said pattern comprises a first set of bits to be inputted to said selector circuits, wherein said pattern further comprises a second set of bits to be stored in memory cells embedded with said selector circuits;
• predecoding a value stored in n-most significant bits of said second register and a value stored in n-most significant bits of said third register to produce a predecode value;
• comparing said predecode value with a value stored in n-most significant bits of said entry of said memory array;
• and
• determining if a stuck-at-fault occurred based on said comparison.

A system, comprising:

• a memory unit operable for storing a computer program for testing stuck-at-faults in circuitry configured to determine matching of memory cell contents;
• and
• a processor coupled to said memory unit, wherein said processor, responsive to said computer program, comprises:
• circuitry operable for loading a first register with a first value, wherein said first register is configured to store contents for a row of a memory array;
• circuitry operable for writing said first value into an entry in said memory array;
• circuitry operable for loading a second register with a second value;
• circuitry operable for loading a third register with one of said second value and a third value, wherein said second and said third values are pre-selected to test selector circuits for stuck-at-faults with a pattern, wherein said selector circuits are configured to determine matching of memory cell contents in said memory array, wherein said pattern comprises a first set of bits to be inputted to said selector circuits, wherein said pattern further comprises a second set of bits to be stored in memory cells embedded with said selector circuits;
• circuitry operable for predecoding a value stored in n-most significant bits of said second register and a value stored in n-most significant bits of said third register to produce a predecode value;
• circuitry operable for comparing said predecode value with a value stored in n-most significant bits of said entry in said memory array;
• and
• circuitry operable for determining if a stuck-at-fault occurred based on said comparison.