US 7,073,100 B2Granted

Method for testing embedded DRAM arrays

AssigneeInternational Business Machines Corporation

InventorsLaura S. Chadwick, William R. Corbin, Jeffrey H. Dreibelbis, Erik A. Nelson, Thomas E. Obremski, Toshiharu Saitoh, Donald L. Wheater

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Abstract

A method and system for testing an embedded DRAM that includes DRAM blocks. The method including: generating a test data pattern in a processor based BIST system, for each DRAM block, performing a write of the test data pattern into the DRAM block, performing a pause for a predetermined period of time, and performing a read of a resulting data pattern from the DRAM block; where for each DRAM block, the write of the test data pattern into the DRAM block is performed before the pause, and the read of the resulting data pattern from each DRAM block is performed after the pause; where at least a portion of the pause of two or more of the DRAM blocks overlap in time; and for each DRAM block comparing the test data pattern to the resulting data pattern.

Claims10

Dependent claims

A method of testing an embedded DRAM, comprising:

generating a test data pattern in a processor based built-in self test system, said built in self test system coupled to said embedded DRAM on a same integrated circuit chip, said embedded DRAM comprised of DRAM blocks;
for each DRAM block of said embedded DRAM, performing a write of said test data pattern into said DRAM block, performing a pause for a predetermined period of time, and performing a read of a resulting data pattern from said DRAM block;
wherein for each DRAM block, said performing said write of said test data pattern into said DRAM block is performed before said performing said pause for said predetermined period of time, and said performing said read of said resulting data pattern from said DRAM block is performed after said performing said pause for said predetermined period of time;
wherein at least a portion of said pause for said predetermined period of time of two or more said DRAM blocks overlap in time;
and
for each DRAM block comparing a data pattern based on said test data pattern to said resulting data pattern.

3 more elements

Dependencies are inferred from the claim text.

Facts

Application: 10/065,694Filed 11 Nov 2002
Published: US 2004/0093539 A113 May 2004
Granted: 4 Jul 2006
Term ends: Not estimatedThe source records don’t support an estimate.

Classification5 codes

G11C 29/12015
Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details: comprising clock generation or timing circuitry
G11C 29/26
Address generation devices; Devices for accessing memories, e.g. details of addressing circuits: accessing multiple arrays
G11C 11/401
Using transistors: forming cells needing refreshing or charge regeneration, i.e. dynamic cells
G11C 2207/104
Aspects relating to interfaces of memory device to external buses: embedded memory devices, e.g. memories with a processing device on the same die…