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US 7,073,099 B1Granted
Method and apparatus for improving memory operation and yield
AssigneeMarvell International Ltd.
InventorsSehat Sutardja, Saeed Azimi
Life of this patent
Estimating the term…
Abstract
A memory circuit includes a memory interface and a first memory that receives a first write address that is associated with first data from said memory interface. A second memory stores addresses of defective memory locations found in said first memory, receives said first write address from said memory interface, compares said first write address to said addresses stored in said memory, and, if a matching address is found, writes said first data to said second memory.
Claims12
A memory circuit comprising:
- a memory interface;
- a first memory that receives a first write address that is associated with first data from said memory interface;
- a second memory that stores addresses of defective memory locations found in said first memory, that receives said first write address from said memory interface, that compares said first write address to said addresses stored in said second memory, and, if a matching address is found, writes said first data to said second memory.
A memory circuit comprising:
- a memory interface;
- first memory means for receiving a first write address that is associated with first data from said memory interface;
- second memory means for storing addresses of defective memory locations found in said first memory means, for receiving said first write address from said memory interface, for comparing said first write address to said addresses stored in said second memory means, and, if a matching address is found, for writing said first data to said second memory means.
Dependencies are inferred from the claim text.