Multi-phase clock generation circuit and clock multiplication circuit
AssigneeSeiko Epson Corporation
InventorMinoru Kozaki
Life of this patent
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Abstract
A circuit is provided to prevent improper locking of a DLL circuit without providing any limitation to the reference clock frequency. By detecting the time difference between edges of multi-phase clocks Ck1–Ck6, a delay time detection signal DT1 corresponding to a delay time 5τ from the multi-phase clock Ck1 to the multi-phase clock Ck6 is generated. An Up1 signal is forcibly output to a charge pump circuit CP1 based on this delay time detection signal DT1, and the output of a Down1 signal is suppressed.
Claims15
A multi-phase clock generation circuit comprising:
- voltage controlled delay elements of N stages connected in cascade wherein N is an integer that is greater than 1;
- delay time control means for controlling a delay time of an output signal of each stage of said voltage controlled delay elements so that a phase of the output signal from the N-th stage of said voltage controlled delay elements matches a phase of a reference clock input in the first stage of said voltage controlled delay elements;
- delay time detection means for receiving time differences between said output signals of each stage and for generating delay time signals corresponding to time differences between output signals of consecutive ones of said stages;
- a delay time monitoring means for receiving said delay time signals and for monitoring the delay time of said voltage controlled delay elements based on said delay time signals;
- and
- a Locking condition control means for controlling a locking condition of the output signals of said voltage controlled delay elements based on a delay time monitoring result by said delay time monitoring means.
A multi-phase clock generation circuit comprising:
- voltage controlled delay elements of N stages connected in cascade, wherein N is an integer that is greater than 1;
- a phase detector circuit for controlling a delay time of an output signal of each stage of said voltage controlled delay elements so that a phase of the output signal from the N-th stage of the voltage controlled delay elements matches a phase of a reference clock input in the first stage of the voltage controlled delay elements;
- a delay time detection circuit for detecting a delay time for K stages (K<N, wherein K is an integer) of said voltage controlled delay elements based on time differences between output signals of consecutive ones of said K stages;
- a delay time decision circuit for deciding if the delay time detected by said delay time detection circuit is within one period of said reference clock;
- and
- a delay time reduction circuit for reducing the delay time to be controlled by said phase detector circuit when the delay time detected by said delay time detection circuit exceeds one period of said reference clock.
A clock multiplication circuit including a multi-phase clock generation circuit for generating multi-phase clocks, and a multiplied clock generation circuit for generating the multiplied clock based on said multi-phase clocks, said multi-phase clock generation circuit comprising:
- voltage controlled delay elements of N stages connected in cascade;
- a phase detector circuit for controlling a delay time of an output signal of each stage of said voltage controlled delay elements so that a phase of the output signal from the N-th stage of said voltage controlled delay elements matches a phase of a reference clock;
- a delay time detection circuit for detecting a delay time for K(K<N) stages of said voltage controlled delay elements based on time differences between output signals of consecutive ones of said K stages;
- a delay time decision circuit for deciding if the delay time detected by said delay time detection circuit is within one period of said reference clock;
- and
- a delay time reduction circuit for reducing the delay time to be controlled by said phase detector circuit when the delay time detected by said delay time detection circuit exceeds one period of said reference clock.
Dependencies are inferred from the claim text.