Data bus arrangement and control method for efficiently compensating for faulty signal lines
AssigneeSamsung Electronics Co., Ltd.
InventorYoung-Soo Jo
Life of this patent
Estimating the term…
Abstract
The present invention discloses a data bus connecting individual modules and carrying data there between. The data bus includes primary signal lines and supplementary signal lines. A master module having a bus monitor and a microprocessor detects for faulty signal lines and substitutes supplementary signal lines for faulty primary signal lines enabling the bus to continue carrying data between modules connected thereto. The status of the signal lines are communicated to all the other modules on the bus by a special signal line on the bus so that each module is informed of the substitution.
Claims25
An apparatus, comprising:
- a data bus comprising:
- a plurality of primary signal lines exclusively used to transmit data between modules connected to said bus in the absence of an inoperable signal line;
- an extra supplemental signal line that remains idle in the absence of an inoperable primary signal line;
- and
- a maintenance signal line used to communicate the presence or absence of an inoperable primary signal line and the implementation of the substitute signal line to carry data to each of said plurality of modules, one of said plurality of modules comprises:
- a bus signal monitor testing for inoperable primary signal lines on said bus;
- and
- a microprocessor communicating results of said test and whether said supplemental signal line has been implemented to carry data to each of said plurality of modules via said maintenance signal line, each module comprises a bus signal selector connecting a bus signal transmitter to the appropriate operable, activated signal lines that carry data based on signals received from said maintenance signal line enabling normal data transfer over said bus between ones of said plurality of modules despite a presence of an inoperable primary signal line.
An apparatus, comprising only one data bus connecting a plurality of modules, said data bus comprising a plurality of primary signal lines and a supplementary signal line, said supplemental signal line being used as a substitute signal line to carry data on said data bus for an inoperable primary signal line only in the presence of an inoperable primary signal line, each of said plurality of modules comprisina only one bus interface unit, each bus interface unit being connected to each of said plurality of primary signal lines as well as the supplementary signal line.
An apparatus, comprising only one data bus connecting a plurality of modules, said data bus comprising a plurality of primary signal lines and a supplementary signal line, said supplemental signal line being used as a substitute signal line to carry data on said data bus for an inoperable primary signal line only in the presence of an inoperable primary signal line, one of said plurality of modules having a bus monitor testing and detecting a presence of an inoperable primary signal line, said one of said plurality of modules further comprising a microprocessor connected to said bus monitor, said microprocessor identifying an inoperable primary signal line if detected and acknowledging that said supplemental signal line is serving as a substitute for said inoperable primary signal line to carry data on said bus when an inoperable primary signal line is detected.
The method of compensating for inoperable signal lines on a data bus connected to a plurality of modules, said method comprising the steps of:
- testing each signal line on said data bus to determine a presence of an inoperable signal line;
- detecting the presence or absence of an inoperable signal line based on said testing step;
- selecting a signal line from a set of extra signal lines on said bus to serve as a substitute signal line for an inoperable signal line to carry data upon detection of said inoperable signal line;
- communicating to each of said plurality of modules an identity of said inoperable signal line and an identity of said selected extra signal line;
- and
- resuming data communication as normal between each of said plurality of modules over said bus using said selected extra signal line.
An apparatus, comprising:
- a data bus having a set of primary signal lines carrying data and a set of extra signal lines that remain idle in the absence of faulty signal lines;
- a plurality of modules connected to said data bus sending and receiving data over said data bus between ones of said plurality of modules;
- a bus monitor detecting a presence of faulty signal lines on said bus;
- a microprocessor selecting substitute signal lines for carrying data from said extra set of signal lines upon detection of a presence of faulty primary signal lines;
- and
- a communication line informing each of said plurality of modules of a presence of faulty signal lines and of a selection of substitute signal lines, wherein each module comprises a signal selector connected to said communication line, said signal selector connecting only signal lines that are presently being used to carry data to a bus signal transmitter used to send and receive data over said bus.
An apparatus, comprising:
- a data bus having a plurality of primary signal lines adapted to carry data and at least one extra signal line adapted to also carry data when at least one of the primary signal lines is faulty;
- and
- a plurality of modules connected to said data bus, each module comprises only one signal selector and only one bus signal transmitter, each signal selector being arranged between the data bus and a corresponding bus signal transmitter, each bus signal transmitter being adatped to send and receive data from both the primary signal lines and the at least one extra signal line when at least one of said primary signal lines is faulty.
Dependencies are inferred from the claim text.