Cascaded microcomputer array and method
AssigneeSilicon Lease, L.L.C.
InventorJerry D. Harthcock
Life of this patent
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Abstract
A microcomputer array and method having a hyper-scalable, real-time monitoring and debug architecture in which several microcomputers are cascaded together into a single, more powerful unit. A cascaded instruction pipeline and related control circuitry allow a plurality of subprocessors or “proto-processors” to be cascaded with the instruction pipeline of a head processor or “nucleus processor” thereby creating an array of processors. The proto-processors may operate independently performing peripheral functions until a cascaded instruction takes priority and causes one or more proto-processors to perform the cascaded instruction and send the results to the nucleus processor. The processors may be microcomputers or Digital Signal Processors (DSPs).
Claims17
An array of microcomputers comprising at least a first microcomputer and a second microcomputer, said array comprising:
- a compound instruction register within the first microcomputer for receiving a first compound instruction that includes a cascade operation code (opcode) that, upon decoding, indicates whether the first instruction is to be sent to the second microcomputer in the array for execution;
- decode logic within the first microcomputer that fetches and decodes the first compound instruction from the register;
- a cascaded instruction pipeline for sending the first instruction to the second microcomputer for execution when the decoded cascade opcode indicates that the first instruction is to be sent to the second microcomputer;
- execution logic within the second microcomputer that executes the first instruction and determines a result;
- and
- a cascade response bus for sending the result from the second microcomputer to the first microcomputer;
- wherein the second microcomputer executes an application program until a compound instruction is received from the first microcomputer indicating that the second microcomputer is to execute the instruction, said compound instruction having priority over the application program.
A hyper-scalable microcontroller comprising:
- a nucleus processor;
- a cascaded instruction pipeline;
- a plurality of proto-processors connected to the nucleus processor through the cascaded instruction pipeline;
- and
- control circuitry that selectively causes each of the plurality of proto-processors to operate independently or as an extension of the nucleus processor, wherein the control circuitry causes the nucleus processor to send a plurality of cascaded instructions to the proto-processors through the cascaded instruction pipeline, each of said instructions including an indication of which of the plurality of proto-processors is to execute each instruction,
- wherein at least one of the cascaded instructions includes an indication that a plurality of the pinto-processors are to execute the instruction.
A method of controlling a plurality of microprocessors comprising the steps of:
- connecting at least one proto-processor to a nucleus processor through a cascaded instruction pipeline, said at least one proto-processor executing an application program stored either internally or externally to the proto-processor;
- and
- selectively causing the at least one proto-processor to operate independently or as an extension of the nucleus processor by sending from the nucleus processor, at least one cascaded compound instruction to the at least one proto-processor through the cascaded instruction pipeline, wherein the at least one compound instruction includes a cascade operation code (opcode) that indicates which of the at least one proto-processors is to execute the instruction, wherein when a proto-processor receives a compound instruction indicating that the receiving proto-processor is to execute the instruction, the receiving proto-processor suspends execution of its application program and executes the received instruction.
Compound instruction logic in a nucleus processor for registering, decoding, and executing a compound instruction, said compound instruction logic comprising:
- means for fetching and registering the compound instruction;
- means for decoding the compound instruction and determining whether the compound instruction is a cascade instruction;
- means responsive to a determination that the compound instruction is a cascade instruction, for presenting the compound instruction in a partially decoded form to associated autonomous proto-processors via a cascaded instruction pipeline, said cascade instruction causing the autonomous proto-processors to temporarily suspend operation of their own programs and to execute the cascade instruction;
- and
- means for receiving processing results resulting from the execution of the cascade instruction by the autonomous proto-processors, and for loading the results into a working (W) register without utilizing Direct Memory Access (DMA) circuitry or interrupts.
Dependencies are inferred from the claim text.