US 7,073,047 B2Granted

Control chip and method for accelerating memory access

AssigneeVIA Technologies, Inc.

InventorsKuang-Kai Kuo, Kuo-Ping Liu

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Abstract

A control chip and operating method for accelerating memory access that can be applied to a memory system whose memory read command actual address is read from a system bus in a number of synchronous transmissions. On receiving a first section read address, the control chip operates to compare the first section read address with an identical bit portion of the write address of the memory-write commands inside a memory-write command queue. If the comparison indicates some difference, permission for executing the memory read command is granted. If the comparison indicates the presence of identical bits, a second section read address is received and compared with an identical bit portion of the write address of the memory-write commands inside a memory-write command queue. If the comparison indicates some difference, permission for executing the memory read command is granted. If the comparison indicates the presence of identical bits, permission for executing the memory read command is granted only after the memory-write command inside the memory-write command queue having an identical write address is executed.

Claims10

Dependent claims

A control chip for accelerating memory access, wherein said control chip is coupled to a system bus at least having a clocking line, said control chip comprising:

a memory write command queue for holding a plurality of memory write commands, wherein each said memory write command has a write address;
a bus interface unit coupled to the system bus, wherein said bus interface unit receives a first section read address and a second section read address of a memory read command sequentially from said system bus according to a clock signal and concurrently outputs said first section read address and said second section read address;
and
a memory request organizer coupled to the bus interface unit and said memory write command queue for comparing said first section read address with an identical bit portion of each said write address of said memory-write commands inside said memory-write command queue;
wherein if the comparison indicates a difference, execution of said memory read command would be permitted;
if the comparison indicates the presence of identical bits, said second section read address would be compared with an identical bit portion of each said write address of said memory-write commands inside said memory-write command queue;
wherein if the comparison indicates a difference, execution of said memory read command would be permitted;
if said comparison still indicating said presence of identical bits, permission to execute said memory read command would be delayed until the memory-write command with identical address bits inside said memory-write command queue executes;
wherein said first section read address and said second section read address are compared respectively before they are combined.

6 more elements

A method of operating a control chip for accelerating memory access wherein said control chip couples with a system bus and includes at least a memory-write command queue for holding a plurality of memory-write commands with each said memory write command further including a write address, said method comprising the steps of:

receiving a first section read address transmitted through said system bus;
comparing said first section read address with an identical bit portion of each said write address of said memory-write commands inside said memory-write command queue;
if the comparison indicates some difference, permitting execution of a memory read command associated with the first section read address;
receiving a second section read address transmitted through said system bus;
comparing said second section read address with an identical bit portion of each said write address of said memory-write commands inside said memory-write command queue, and
if the comparison indicates some difference, permitting said execution of said memory read command;
and
if the comparison indicates a presence of identical bits, waiting until said memory-write command inside said memory-write command queue, having an identical write address is executed before permitting said execution of said memory read command;
wherein said first section read address and said second section read address are compared respectively before they are combined.

6 more elements

Dependencies are inferred from the claim text.