Method and apparatus for sharing TLB entries

A processing system providing operating-system transparent sharing of virtual address translations, the processing system comprising:

• a first logical processor;
• a second logical processor;
• a storage location to store a virtual address translation;
• and
• a control logic to access a first virtual address translation for the first logical processor in the storage location and to transparently produce a first sharing indication if the virtual address translation may be shared with the second logical processor.

A multithreading processor comprising:

• an address translation stage including a translation lookaside buffer having a plurality of entries to translate virtual addresses to physical addresses;
• a first entry of the plurality of entries to translate a first virtual address for a first process;
• a control logic comprising circuitry to identify a sharability of the first entry;
• the control logic further to provide a first sharing indication to indicate if the first entry may be shared by a second process;
• and
• a sharing indication field in the first entry to store the first sharing indication provided by the control logic.