Multiprocessor system supporting multiple outstanding TLBI operations per partition
AssigneeInternational Business Machines Corporation
InventorsRavi Kumar Arimilli, Guy Lynn Guthrie, Kirk Samuel Livingston
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Abstract
Disclosed is a symmetric multiprocessor data processing system (SMP) that implements a TLBI protocol, which enables multiple TLBI operations from multiple processors within a partition to complete concurrently. Thus, a global TLB lock, synchronization, and TLB unlock is not necessary. When a TLBI instruction is executed, the master dynamically manages the behavior of the TLBI operation based on asynchronously snooping another TLBI. If concurrent TLBI management is required, then the master dynamically degrades the TLBI to a “barrier” class instruction.
Claims20
A multiprocessor data processing system (MP) comprising:
- a plurality of processors including a first processor and a second processor coupled together by an interconnect, wherein each processor comprises a cache coherency subsystem including a translation look-aside buffer (TLB), at least one execution unit and an associated execution queue, wherein said execution queue holds queue address instructions with real addresses translated from corresponding virtual address by said TLB;
- a memory coupled to said plurality of processors by said interconnect and which includes a page frame table (PFT) in which is stored a plurality of page table entries (PTEs) of virtual and real address translation pairs;
- operating logic associated with each processor for implementing a TLB invalidate (TLBI) response protocol that controls a response by each of said plurality of processors to receipt of TLBIs;
- and
- wherein, responsive to receipt of a TLBI by said first processor generated in response to a page fault at the PFT associated with a memory access operation of the first processor, said TLBI response protocol triggers said first processor to first drain queued address instructions from the execution queue of each of said at least one execution unit of said first processor before issuing said TLBI out on the interconnect, wherein said TLBI is snooped on the interconnect by the second processor only after draining of the execution queue has completed at said first processor.
A method in a multiprocessor data processing system (MP) with a first processor and second processor for handling concurrent translation look-aside buffer invalidates (TLBIs) from said first processor and said second processor, said method comprising:
- responsive to a receipt at said first processor of a TLBI generated in response to a page fault associated with a memory access operation of the first processor, immediately suspending execution of instructions at a cache coherency subsystem of said first processor;
- invalidating a corresponding entry in a translation look-aside buffer (TLB) of said first processor;
- draining all execution queues at said cache coherency subsystem of said first processor;
- and
- issuing said TLBI out to a system interconnect only after said execution queues have completed draining, wherein all queued address instructions are drained before issuing said TLBI out on the interconnect, and wherein the second processor on said interconnect snoops said TLBI on the interconnect only after draining of the execution queue has completed at said first processor.
A processing unit for utilization within a multi-processor system having multiple processors connected via an interconnect, said processing unit comprising:
- one or more execution units each having a corresponding execution queue associated therewith by which instructions having a translated real address are scheduled for execution by the corresponding execution unit;
- and
- a cache coherency subsystem connected to the execution queues of the one or more execution units, said cache coherency subsystem comprising:
- a translation look-aside buffer (TLB) and associated TLB controller;
- means for receiving instructions for executing at said executing unit, said instructions including a TLB invalidate (TLBI) generated in response to a page fault associated with a memory access operation of the processing unit;
- and
- processing logic, responsive to a receipt of said TLBI, for implementing a TLBI response protocol that triggers a sequence of operations comprising:
- (1) first draining each execution queue of said processing unit and (2) then issuing said TLBI out on an interconnect mechanism.
Dependencies are inferred from the claim text.