Providing a register file memory with local addressing in a SIMD parallel processor
AssigneeMicron Technology, Inc.
InventorGraham Kirsch
Life of this patent
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Abstract
A degree of local addressing is provided for a processing element array by partitioning a register file memory (e.g., data columns, data rows), and adding a select column or row to be associated with each block. The select column or row allows each processing element to read data from or to write data to a different register file address. Global addressing may also be implemented by reading data from or writing data to the same register file address for each processing element. The invention provides the advantage of faster overall execution time. In addition, there is minimal additional area overhead because of the need to pitch match the processing element array to a main memory.
Claims54
For use in a memory with global addressing and local addressing, wherein said global addressing allows a plurality of processing elements to read data from or to write data to a location in said memory and said local addressing allows said plurality of processing elements to read data from or to write data to different locations in said memory, apparatus for providing said local addressing comprising:
- a decoder comprising:
- n inputs coupled to receive one bit each of an address from which data is to be read or to which data is to be written, and
- 2n outputs;
- a plurality of select columns in said memory, wherein each of said plurality of select columns comprises a plurality of select cells, wherein each of said plurality of select cells comprises:
- a first input coupled to receive one of said 2n outputs of said decoder via a master row select line,
- a second input coupled to receive a value from a select cell write line, and
- an output;
- a plurality of AND gates, wherein each of said plurality of AND gates comprises:
- a first input coupled to receive an output of a select cell,
- a second input coupled to receive a value from a corresponding master row select line, and
- an output;
- and
- a plurality of data columns in said memory, wherein each of said plurality of data columns comprises a plurality of rows of data cells, each row of data cells corresponds to one select cell and each row of data cells comprises:
- an input coupled to receive an output of a corresponding AND gate, and
- a data path from which data is to be read or to which data is to be written.
For use in a memory with global addressing and local addressing, wherein said global addressing allows a plurality of processing elements to read data from or to write data to a location in said memory and said local addressing allows said plurality of processing elements to read data from or to write data to different locations in said memory, apparatus for providing said local addressing comprising:
- a register file memory, wherein said register file memory allows each of said plurality of processing elements to read data from or to write data to a different address in said register file memory;
- a control logic sequencer, wherein said control logic sequencer controls data flow;
- an interconnect, wherein said interconnect allows data flow between said plurality of processing elements;
- and
- a memory buffer register, wherein said memory buffer register stores data from said plurality of processing elements to send to a main memory and stores data from said main memory to send to said plurality of processing elements.
Dependencies are inferred from the claim text.