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US 7,073,030 B2Granted
Method and apparatus providing non level one information caching using prefetch to increase a hit ratio
AssigneeInternational Business Machines Corporation
InventorsMichael Joseph Azevedo, Carol Spanel, Andrew Dale Walls
Life of this patent
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Abstract
A method and apparatus for increasing the processing speed of processors and increasing the data hit ratio is disclosed herein. The method increases the processing speed by providing a non-L1 instruction caching that uses prefetch to increase the hit ratio. Cache lines in a cache set are buffered, wherein the cache lines have a parameter indicating data selection characteristics associated with each buffered cache line. Then which buffered cache lines to cast out and/or invalidate is determined based upon the parameter indicating data selection characteristics.
Claims20
An information caching method comprising:
- storing data for processing by a processor in a cache set for storing,
- setting a set of indicators for the cache set, the set of indicators including a parameter indicating whether the cache line has been prefetched but not requested by the processor, a parameter indicating whether the cache line is valid and a rank flag used for ranking cache lines for being cast out;
- and
- storing data that is prefetched in a prefetch buffer, the prefetch buffer being associated with the cache set, wherein the prefetch buffer includes a fetch tag for indicating a cache line in the prefetch buffer has been fetched by the processor directly thereby bypassing the cache set,
- delivering to the processor data having an address tag matching a data request from the processor;
- and
- determining which cache line in the cache set to cast out and/or invalidate based upon an analysis of the set of indicators of the cache set.
4 more elements
A processing apparatus comprising:
- at least one processor for requesting data matching an address tag;
- a memory;
- a cache controller;
- and
- a cache hierarchy, comprising;
- a cache set for storing data for processing by a processor, wherein the cache set includes a set of indicators for the cache set, the set of indicators including a parameter indicating whether the cache line has been prefetched but not requested by the processor, a parameter indicating whether the cache line is valid and a rank flag used for ranking cache lines for being cast out;
- and
- a prefetch buffer for storing data that is prefetched, the prefetch buffer being associated with the cache set, wherein the prefetch buffer includes a fetch tag for indicating a cache line in the prefetch buffer has been fetched by the processor directly thereby bypassing the cache set,
- wherein the cache controller delivers data having an address tag matching the data request to the at least one processor and determining which cache line in the cache set to cast out and/or invalidate based upon an analysis of the set of indicators of the cache set.
6 more elements
An information caching system comprising:
- means for requesting data matching an address tag;
- means for storing data;
- means for providing data caching;
- means for controlling the means for providing data caching;
- wherein the means for providing data caching further comprises;
- means for storing data for processing by the means for requesting data, wherein the means for storing data for processing by the means for requesting data includes means for indicating whether the cache line has been prefetched but not requested by the means for requesting data, means for indicating whether the cache line is valid and means for ranking cache lines for being cast out;
- and
- means for storing data that is prefetched, the means for storing data that is prefetched being associated with the means for storing data for processing by the means for requesting data, wherein the means for storing data that is prefetched includes means for indicating a cache line in the prefetch buffer has been fetched by the means for processing directly thereby bypassing the means for storing data for processing by the means for requesting data,
- wherein means for controlling the means for providing data caching further comprises means for delivering data having an address tag matching the data request to the means for requesting data and for determining which cache line in the means for storing data for processing to cast out and/or invalidate based upon an analysis of the means for indicating whether the cacheline has been prefetched but not requested by the means for requesting data, means for indicating whether the cache line is valid and means for ranldng cache lines for being cast out.
6 more elements
An article of manufacture comprising a program storage medium readable by a computer, the medium tangibly embodying one or more programs of instructions executable by the computer to perform an instruction caching method, the method comprising:
- storing data for processing by a processor in a cache set for storing,
- setting a set of indicators for the cache set, the set of indicators including a parameter indicating whether the cache line has been prefetched but not requested by the processor, a parameter indicating whether the cache line is valid and a rank flag used for ranking cache lines for being cast out;
- and
- storing data that is prefetched in a prefetch buffer, the prefetch buffer being associated with the cache set, wherein the prefetch buffer includes a fetch tag for indicating a cache line in the prefetch buffer has been fetched by the processor directly thereby bypassing the cache set,
- delivering to the processor data having an address tag matching a data request from the processor;
- and
- determining which cache line in the cache set to cast out and/or invalidate based upon an analysis of the set of indicators of the cache set.
4 more elements
Dependencies are inferred from the claim text.